MAX1396ETB+T Maxim Integrated Products, MAX1396ETB+T Datasheet - Page 16

IC ADC 12BIT 312.5KSPS 10-TDFN

MAX1396ETB+T

Manufacturer Part Number
MAX1396ETB+T
Description
IC ADC 12BIT 312.5KSPS 10-TDFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1396ETB+T

Number Of Bits
12
Sampling Rate (per Second)
312.5k
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
830µW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-WFDFN Exposed Pad
Number Of Adc Inputs
2
Architecture
SAR
Conversion Rate
312 KSPs
Resolution
12 bit
Interface Type
Serial
Voltage Reference
External
Supply Voltage (max)
3.3 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MAX1396ETB+T
1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 12-Bit, SAR ADCs
The MAX1393/MAX1396 sample data on the falling
edge of its third SCLK cycle (Figure 14). In actuality,
there is a small delay between the falling edge of the
sampling clock and the actual sampling instant.
Aperture delay (t
falling edge of the sampling clock and the instant when
an actual sample is taken.
Aperture jitter (t
the aperture delay (Figure 14).
DC PSRR is defined as the change in the positive full-
scale transfer function point caused by a full range vari-
ation in the analog power-supply voltage (V
TRANSISTOR COUNT: 9106
PROCESS: BiCMOS
16
DC Power-Supply Rejection Ratio (PSRR)
______________________________________________________________________________________
AJ
AD
) is the sample-to-sample variation in
) is the time defined between the
Chip Information
Aperture Delay
Aperture Jitter
DD
).
Figure 14. T/H Aperture Timing
(INTERNAL
SAMPLED
DIFFERENTIAL
VOLTAGE
*INDICATES THE MAX1396 ONLY.
ANALOG
SIGNAL)
INPUT
VOLTAGE
REF
INPUT
SCLK
INPUT
DATA
2 x AA CELLS
T/H
0.1μF
+
TRACK
-
Typical Operating Circuit
0.1μF
REF
AIN+
(AIN1)*
AIN-
(AIN2)*
THIRD FALLING EDGE
t
AD
t
AJ
HOLD
MAX1393
MAX1396
GND
V
DD
(CH1/CH2)*
UNI/BIP
DOUT
SCLK
CS
OE
SS
SCL
MISO
CPU

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