MAX191BCNG+ Maxim Integrated Products, MAX191BCNG+ Datasheet - Page 18

• Manufacturer Part Number: MAX191BCNG+
• Description: IC ADC 12BIT 100KSPS W/REF 24DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX191BCNG+

• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: MICROWIRE™, Parallel, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.07W
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 1067 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Following the data transfer, the DSP receive shift regis-
ter (RSR) contains a 16-bit word consisting of the 12
data bits, MSB first, followed by four trailing 0s.
When the +5V power supply is first applied to the
MAX191, perform a single conversion to initialize the
ADC (the BUSY signal status is undefined at power-on).
Disregard the data outputs.
In some battery-powered systems, it is desirable to
power down or remove power from the ADC during
inactive periods. To power down the MAX191, drive PD
low. In this mode, all internal ADC circuitry is off except
the reference, and the ADC consumes less than 50µA
max (assuming all signals CS, RD, CLK, and HBEN are
static and within 200mV of the supplies). Figure 17
shows a practical way to drive the PD pin. If using inter-
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
Figure 17. Drive Circuits for PD Pin
18
______________________________________________________________________________________
a. INTERNAL-REFERENCE COMPENSATION MODE
b. EXTERNAL-REFERENCE COMPENSATION MODE
Applications Information
OPEN-DRAIN
BUFFER
1
1
Power-On Initialization
PD
PD
Power-Down Mode
MAX191
MAX191
nal reference compensation, drive PD between V
and DGND with a µP I/O pin or other logic device
(Figure 17a). For external-reference compensation
mode, use the circuit in Figure 17b to drive PD between
DGND and the floating voltage of PD. An alternative is
to drive PD with three-state logic or a switch, provided
the off leakage does not exceed 100nA.
The internal 4.096V reference is available at VREF and
must be bypassed to AGND with a 4.7µF low-ESR
capacitor (less than 1/2Ω) in parallel with a 0.1µF capaci-
tor, unless internal-reference compensation mode is
used (see the Internal Reference Compensation section).
This minimizes noise and maintains a low reference
impedance at high frequencies. The reference output
can be disabled by connecting REFADJ to V
using an external reference.
Power-down performance can be optimized for a given
conversion rate by selecting either internal or external
reference compensation.
The connection for internal compensation is shown in
Figure 18a. In this mode, the reference stabilizes quick-
ly enough so that a conversion typically starts within
35µs after the ADC is reactivated (PD pulled high). In
this compensation mode, the reference buffer requires
longer recovery time from SAR transients, therefore
requiring a slower clock (and conversion time). With
internal reference compensation, the typical conversion
time rises to 25µs (Figure 18b). Figure 18c illustrates
the typical average supply current vs. conversion rate,
Figure 18a. Internal-Compensation Mode Circuit
0.1 F
Reference-Compensation Modes
+5V
1
5
6
PD
VREF
REFADJ
Internal Reference
Internal Compensation
MAX191
DD
when
DD