CS5345-CQZR Cirrus Logic Inc, CS5345-CQZR Datasheet - Page 34

• Manufacturer Part Number: CS5345-CQZR
• Description: IC ADC AUD 105DB 200KHZ 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5345-CQZR

• Package / Case: 48-LQFP
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 485mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPs
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 3.13 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1780 - EVALUATION BOARD FOR CS5345
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

34
6.7
6.7.1
6.8
6.8.1
Reserved
Reserved
7
7
Channel A PGA Control - Address 08h
ADC Input Control - Address 09h
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See
ample settings.
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See
Table
Reserved
Reserved
6
6
11.
Reserved
Table
Gain5
Table 10. Example Gain and Attenuation Settings
5
5
11.
Gain[5:0]
101000
000000
011000
PGASoft
Gain4
4
4
Table
PGAZero
Gain3
11.
3
3
Setting
+12 dB
-12 dB
0 dB
Gain2
Sel2
2
2
Gain1
Sel1
1
1
Table 10
CS5345
Gain0
DS658F2
Sel0
0
for ex-
0