AD7927BRUZ Analog Devices Inc, AD7927BRUZ Datasheet - Page 4

• Manufacturer Part Number: AD7927BRUZ
• Description: IC ADC 12BIT 8CH 200KSPS 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7927BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Number Of Converters: 1
• Power Dissipation (max): 7.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 200kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 1.5mA
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 200KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: No
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 7.5mW
• Differential Linearity Error: -0.9LSB/1.5LSB
• Integral Nonlinearity Error: ±1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7927CBZ - BOARD EVALUATION FOR AD7927
• Lead Free Status / Rohs Status: Compliant

AD7927
TIMING SPECIFICATIONS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
Sample tested at 25∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AV
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ¥ V
t
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
11
12
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the timing characteristics t
of the part and is independent of the bus loading.
8
3
3
4
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
2
AV
10
20
16 ¥ t
50
10
35
40
0.4 ¥ t
0.4 ¥ t
10
15/45
10
5
20
1
DD
SCLK
SCLK
SCLK
= 3 V
Limit at T
Figure 1. Load Circuit for Digital Output Timing Specifications
AV
10
20
16 ¥ t
50
10
30
40
0.4 ¥ t
0.4 ¥ t
10
15/35
10
5
20
1
1
MIN
DD
(AV
SCLK
, T
SCLK
SCLK
= 5 V
DD
MAX
= 2.7 V to 5.25 V, V
AD7927
OUTPUT
PIN
ns min/max
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ms max
TO
50pF
C
L
DRIVE
200 A
200 A
–4–
AV
I
I
DD
OL
OH
SCLK Falling Edge to DOUT High Impedance
Description
Minimum Quiet Time Required between CS Rising Edge
and Start of Next Conversion
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to DOUT Valid Hold Time
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/Auto
Shutdown Mode
, REF
IN
1.6V
= 2.5 V, T
A
= T
DD
DRIVE
) and timed from a voltage level of 1.6 V.
MIN
.
to T
MAX
, unless otherwise noted.)
8
, is the true bus relinquish time
REV. 0