AD7323BRUZ Analog Devices Inc, AD7323BRUZ Datasheet - Page 29

• Manufacturer Part Number: AD7323BRUZ
• Description: IC ADC 12BIT+ SAR 4CHAN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7323BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 17mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 500kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7323CBZ - BOARD EVALUATION FOR AD7323CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DOUT
MODES OF OPERATION
The AD7323 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7323 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance
with the AD7323 being fully powered up at all times. Figure 46
shows the general operation of the AD7323 in normal mode.
The conversion is initiated on the falling edge of CS , and the
track-and-hold section enters hold mode, as described in the
Serial Interface
transfer is loaded into one of the on-chip registers if the write
bit is set. The register is selected by programming the register
select bits (see
SCLK
DIN
CS
SDATA
SCLK
PART IS IN FULL
SHUTDOWN
DIN
CS
Table 8
1
section. Data on the DIN line during the 16 SCLK
DATA INTO CONTROL/SEQUENCE/RANGE REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT +
1
).
Figure 46. Normal Mode
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
CONVERSION RESULT
DATA INTO CONTROL REGISTER
PM1 = 0, PM0 = 0
INVALID DATA
16
Figure 47. Exiting Full Shutdown Mode
16
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t
POWER-UP
The AD7323 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result,
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, t
FULL SHUTDOWN MODE (PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7323 is powered
down. The part retains information in the registers during full
shutdown. The AD7323 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
A write to the control register with PM1 = 1 and PM0 = 1 places
the part into full shutdown mode. The AD7323 enters full shut-
down mode on the 15
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15
updated. Figure 47 shows how the AD7323 is configured to exit
full shutdown mode. To ensure the AD7323 is fully powered up,
t
THE PART IS FULLY POWERED UP
ONCE
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
POWER-UP
1
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
t
POWER-UP
should elapse before the next CS falling edge.
th
SCLK rising edge once the control register is
DATA INTO CONTROL REGISTER
HAS ELAPSED
IN CONTROL REGISTER
th
SCLK rising edge once the control register
QUIET
, has elapsed.
16
AD7323