AD7323BRUZ Analog Devices Inc, AD7323BRUZ Datasheet - Page 32

• Manufacturer Part Number: AD7323BRUZ
• Description: IC ADC 12BIT+ SAR 4CHAN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7323BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 17mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 500kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7323CBZ - BOARD EVALUATION FOR AD7323CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7323
SERIAL INTERFACE
Figure 51 shows the timing diagram for the serial interface of
the AD7323. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7323 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. When the conversion is initiated, it
requires 16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
rising edge. On the 16
to three-state. If the rising edge of CS occurs before 16 SCLK
cycles have elapsed, the conversion is terminated, and the
DOUT line returns to three-state. Depending on where the CS
signal is brought high, the addressed register may be updated.
DOUT
SCLK
DIN
CS
THREE-
STATE
th
SCLK falling edge, the DOUT line returns
WRITE
ZERO
t
2
1
2 IDENTIFICATION BITS
t
ADD1
3
t
SEL1
9
REG
2
ADD0
SEL2
REG
Figure 51. Serial Interface Timing Diagram (Control Register Write)
3
SIGN
MSB
4
DB11
t
t
6
4
t
CONVERT
th
t
10
5
SCLK
t
DB10
7
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Data is clocked into the AD7323 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is being addressed. The control register is a 12-bit register. If the
control register is addressed by the three MSBs, the data on the
DIN line is loaded into the control on the 15
edge. If the sequence register or the range register is addressed,
the data on the DIN line is loaded into the addressed register on
the 11
Conversion data is clocked out of the AD7323 on each SCLK
falling edge. Data on the DOUT line consists of a zero bit, two
channel identifier bits, a sign bit, and a 12-bit conversion result.
The channel identifier bits are used to indicate which channel
corresponds to the conversion result. The zero bit is clocked out
on the CS falling edge, and the ADD1 bit is clocked out on the
first SCLK falling edge.
DB2
14
t
5
th
DB1
SCLK falling edge.
LSB
15
DB0
DON’T
CARE
16
THREE-STATE
t
8
t
QUIET
t
1
th
SCLK falling