KAD5512P-17Q72 Intersil, KAD5512P-17Q72 Datasheet - Page 21

• Manufacturer Part Number: KAD5512P-17Q72
• Description: IC ADC 12BIT 170MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-17Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 253mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This relationship shows the SNR that would be achieved
if clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal
aperture jitter is the uncertainty in the sampling instant
shown in Figure 3. The internal aperture jitter combines
with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or
single data rate (SDR) formats. The even numbered data
output pins are active in DDR mode in the 72 pin
package option. When CLKOUT is low the MSB and all
odd logical bits are output, while on the high phase the
LSB and all even logical bits are presented (this is true in
both the 72 pin and 48 pin package options). Figures 3
and 4 show the timing relationships for LVDS/CMOS and
DDR/SDR modes.
The 48-QFN package option contains six LVDS data
output pin pairs, and therefore can only support DDR
mode.
Additionally, the drive current for LVDS mode can be set
to a nominal 3mA or a power-saving 2mA. The lower
current setting can be used in designs where the receiver
is in close physical proximity to the ADC. The applicability
of this setting is dependent upon the PCB layout,
therefore the user should experiment to determine if
performance degradation is observed.
SNR
100
95
90
85
80
75
70
65
60
55
50
1
=
20 log
FIGURE 32. SNR vs CLOCK JITTER
tj = 100ps
10
⎛
⎝
------------------- -
2πf
1
IN
INPUT FREQUENCY (MHz)
t
10
J
⎞
⎠
tj = 10ps
21
tj = 1ps
tj = 0.1ps
100
10 BITS
14 BITS
12 BITS
(EQ. 1)
KAD5512P
1000
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details
on this are contained in “Serial Peripheral Interface” on
page 24.
An external resistor creates the bias for the LVDS drivers.
A 10kΩ, 1% resistor must be connected from the RLVDS
pin to OVSS.
Over Range Indicator
The over range (OR) bit is asserted when the output
code reaches positive full-scale (e.g. 0xFFF in offset
binary mode). The output code does not wrap around
during an over-range condition. The OR bit is updated at
the sample rate.
Power Dissipation
The power dissipated by the KAD5512P is primarily
dependent on the sample rate and the output modes:
LVDS vs. CMOS and DDR vs SDR. There is a static bias in
the analog supply, while the remaining power dissipation
is linearly related to the sample rate. The output supply
dissipation is approximately constant in LVDS mode, but
linearly related to the clock frequency in CMOS mode.
Figures 36 and 37 illustrate these relationships.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required.
Two power saving modes are available: Nap, and Sleep.
Nap mode reduces power dissipation to less than 95mW
and recovers to normal operation in approximately 1µs.
Sleep mode reduces power dissipation to less than 6mW
but requires approximately 1ms to recover from a sleep
command.
Wake-up time from sleep mode is dependent on the state
of CSB; in a typical application CSB would be held high
during sleep, requiring a user to wait 150µs max after
CSB is asserted (brought low) prior to writing ‘001x’ to
SPI Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
OUTMODE PIN
TABLE 2. OUTMODE PIN SETTINGS
AVDD
AVSS
Float
LVDS, 3mA
LVDS, 2mA
LVCMOS
MODE
October 1, 2010
FN6807.4