KAD5512P-17Q72 Intersil, KAD5512P-17Q72 Datasheet - Page 27

• Manufacturer Part Number: KAD5512P-17Q72
• Description: IC ADC 12BIT 170MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-17Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 253mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Internal clock signals are generated by a delay-locked
loop (DLL), which has a finite operating range. Table 14
shows the allowable sample rate ranges for the slow and
fast settings.
.
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
of setting these options is different from the other
registers.
The procedure for setting output_mode_B is shown in
Figure 42. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The KAD5512 can produce preset or user defined
patterns on the digital outputs to facilitate in-site testing.
A static word can be placed on the output bus, or two
different words can alternate. In the alternate mode, the
values defined as Word 1 and Word 2 (as shown in
Table 15) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
DLL RANGE
OUTPUT_MODE_B
This bit sets the DLL operating range to fast (default)
or slow.
CONFIG_STATUS
FIGURE 42. SETTING OUTPUT_MODE_B REGISTER
Slow
Fast
READ
READ
0x74
0x75
TABLE 13. OUTPUT FORMAT CONTROL
VALUE
000
001
010
100
TABLE 14. DLL RANGES
DESIRED
MIN
VALUE
40
80
27
f
S
MAX
100
OUTPUT FORMAT
Two’s Complement
MAX
Offset Binary
0x93[2:0]
Pin Control
Gray Code
WRITE TO
UNIT
MSPS
MSPS
0x74
KAD5512P
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 17.
ADDRESS 0XC2: USER_PATT1_LSB AND
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB AND
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
72 Pin/48 Pin Package Options
The KAD5512 is available in both 72 pin and 48 pin
packages. The 48 pin package option supports LVDS DDR
only. A reduced set of pin selectable functions are
available in the 48 pin package due to the reduced
pinout; (OUTMODE, OUTFMT, and CLKDIV pins are not
available). Table 16 shows the default state for these
functions for the 48 pin package. Note that these
functions are available through the SPI, allowing a user
to set these modes as they desire, offering the same
flexibility as the 72 pin package option. DC and AC
performance of the ADC is equivalent for both package
options.
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
VALUE
TABLE 16. 48 PIN SPI - ADDRESSABLE FUNCTIONS
FUNCTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
OUTMODE
OUTFMT
CLKDIV
TABLE 15. OUTPUT TEST MODES
OUTPUT TEST MODE
Negative Full-Scale
Positive Full-Scale
Checkerboard
DESCRIPTION
User Pattern
0xC0[3:0]
Output Driver
Clock Divider
One/Zero
Reserved
Reserved
Data Coding
Midscale
Off
Mode
user_patt1 user_patt2
WORD 1
Two’s Complement
0xAAAA
0x8000
0x0000
LVDS, 3mA (DDR)
DEFAULT STATE
0xFFFF
0xFFFF
N/A
N/A
Divide by 1
October 1, 2010
WORD 2
0x5555
0x0000
N/A
N/A
N/A
N/A
N/A
FN6807.4