MAX114EAG+ Maxim Integrated Products, MAX114EAG+ Datasheet - Page 8

• Manufacturer Part Number: MAX114EAG+
• Description: IC ADC 8BIT 1MSPS 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX114EAG+

• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Data Interface: Parallel
• Number Of Converters: 3
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In read mode, WR/RDY is configured as a status output
(RDY), so it can drive the ready or wait input of a µP.
RDY is an open-collector output (no internal pull-up)
that goes low after the falling edge of CS and goes high
at the end of the conversion. If not used, the WR/RDY
pin can be left unconnected. The INT output goes low
at the end of the conversion and returns high on the ris-
ing edge of CS or RD.
Figures 4 and 5 show the operating sequence for write-
read mode. The comparator inputs track the analog
input voltage for the duration of t
initiated by a falling edge of WR. When WR returns
high, the result of the four-MSBs flash is latched into the
output buffers and the conversion of the four-LSBs flash
starts. INT goes low, indicating conversion end, and the
lower four data bits are latched into the output buffers.
The data is then accessible after RD goes low (see
Timing Characteristics ).
A minimum acquisition time (t
going low to the start of another conversion (WR going
low).
Options for reading data from the converter include
using internal delay, reading before delay, and pipelined
operation (discussed in the following sections).
The µP waits for the INT output to go low before reading
the data (Figure 4). INT goes low after the rising edge of
WR, indicating that the conversion is complete and the
result is available in the output latch. With CS low, data
outputs D0–D7 can be accessed by pulling RD low. INT
is then reset by the rising edge of CS or RD.
+5V, 1Msps, 4 & 8-Channel,
8-Bit ADCs with 1µA Power-Down
Figure 3. Read Mode Timing (MODE = 0)
8
PWRDN
D0–D7
A0–A2
RDY
INT
_______________________________________________________________________________________
CS
RD
t
ACQ
t
RDY
ADDRESS VALID
t
UP
t
CSS
(N)
Write-Read Mode (MODE = 1)
t
AH
WITH EXTERNAL
t
t
ACCO
CRD
PULL-UP
Using Internal Delay
ACQ
ACQ
) is required from INT
ADDRESS VALID (N + 1)
VALID DATA
. The conversion is
(N)
t
ACQ
t
CSH
t
INTH
t
DH
t
AH
Figure 5 shows an external method of controlling the
conversion time. The internally generated delay (t
varies slightly with temperature and supply voltage,
and can be overridden with RD to achieve the fastest
conversion time. RD is brought low after the rising edge
of WR, but before INT goes low. This completes the
conversion and enables the output buffers that contain
the conversion result (D0–D7). INT also goes low after
the falling edge of RD and is reset on the rising edge of
RD or CS. The total conversion time is therefore: t
t
Figure 4. Write-Read Mode Timing (t
Figure 5. Write-Read Mode Timing (t
D0–D7
RD
A0–A2
D0–D7
A0–A2
INT
WR
CS
RD
WR
INT
+ t
CS
RD
t
ACQ
ACC1
t
CSS
ADDRESS
VALID (N)
t
ADDRESS
VALID (N)
CSS
= 660ns.
t
ACQ
t
AH
t
AH
t
WR
t
WR
t
CSH
t
CSH
t
CWR
t
t
Reading Before Delay
INTL
RD
t
INTL
t
t
ACC1
RD
Fastest Conversion:
t
CSS
t
ACC2
RD
RD
t
CSS
> t
< t
t
ADDRESS VALID (N + 1)
READ1
INTL
ADDRESS VALID (N + 1)
INTL
VALID DATA
t
RI
t
READ2
VALID DATA
(N)
) (MODE = 1)
t
) (MODE = 1)
t
ACQ
ACQ
(N)
t
DH
t
DH
t
t
INTH
CSH
t
CSH
WR
INTL
t
INTH
+
)