AD2S1200YSTZ Analog Devices Inc, AD2S1200YSTZ Datasheet - Page 9

IC CONV R/D 12-BIT W/OSC 44-LQFP

AD2S1200YSTZ

Manufacturer Part Number
AD2S1200YSTZ
Description
IC CONV R/D 12-BIT W/OSC 44-LQFP
Manufacturer
Analog Devices Inc
Type
R/D Converterr
Datasheet

Specifications of AD2S1200YSTZ

Resolution (bits)
12 b
Data Interface
Serial, Parallel
Voltage Supply Source
Analog and Digital
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
44-LQFP
Input Channel Type
Differential
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Voltage Range - Digital
4.75V To 5.25V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD2S1200CBZ - BOARD EVAL FOR AD2S1200
Sampling Rate (per Second)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD2S1200YSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
PRINCIPLE OF OPERATION
The AD2S1200 operates on a Type II tracking closed-loop
principle. The output continually tracks the position of the
resolver without the need for external convert and wait states.
As the resolver moves through a position equivalent to the least
significant bit weighting, the output is updated by one LSB.
The converter tracks the shaft angle θ by producing an output
angle ϕ that is fed back and compared to the input angle θ, and
the resulting error between the two is driven towards 0 when
the converter is correctly tracking the input angle. To measure
the error, S3–S1 is multiplied by Cosϕ and S2–S4 is multiplied
by Sinϕ to give
The difference is taken, giving
This signal is demodulated using the internally generated
synthetic reference, yielding
Equation 3 is equivalent to E
approximately equal to E
where θ − ϕ = angular error.
The value E
of the rotor and the converter’s digital angle output.
A phase-sensitive demodulator, integrators, and a compensation
filter form a closed-loop system that seeks to null the error
signal. When this is accomplished, ϕ equals the resolver angle θ
within the rated accuracy of the converter. A Type II tracking
loop is used so that constant velocity inputs can be tracked
without inherent error.
For more information about the operation of the converter, see
the Circuit Dynamics section.
0
( θ − ϕ) is the difference between the angular error
E
E
E
0
0
Sin
Sin
0
Sin
E
0
ω
ω
(
ω
Sin
t
t
t
×
×
×
0
Cos
θ
Sin
(
( θ − ϕ) for small values of θ − ϕ,
Sin
Cos
Equation 2.
Equation 3.
θ
0
θ
θ
Sin (θ − ϕ), which is
Cos
φ
Sin
Cos
φ
φ
Cos
φ
Cos
θ
Sin
S
S
θ
1
2
Sin
φ
to
to
)
φ
S
S
)
4
3
Rev. 0 | Page 9 of 24
FAULT DETECTION CIRCUIT
The AD2S1200 fault detection circuit will detect loss of resolver
signals, out of range input signals, input signal mismatch, or loss
of position tracking. In these cases, the position indicated by the
AD2S1200 may differ significantly from the actual shaft
position of the resolver.
Monitor Signal
The AD2S1200 generates a monitor signal by comparing the
angle in the position register to the incoming Sin and Cos
signals from the resolver. The monitor signal is created in a
similar fashion to the error signal described in the Principle of
Operation section. The incoming signals Sin θ and Cos θ are
multiplied by the Sin and Cos of the output angle, respectively,
and then added together as shown below:
Where A1 is the amplitude of the incoming Sin signal (A1 ×
Sin θ ), A2 is the amplitude of the incoming Cos signal (A2 ×
Cos θ ), θ is the resolver angle, and ϕ is the angle stored in the
position register. Note that Equation 4 is shown after demodula-
tion, with the carrier signal Sin ω t removed. Also note that for
matched input signal (i.e., no-fault condition), A1 = A2.
When A1 = A2 and the converter is tracking ( θ = ϕ), the
monitor signal output has a constant magnitude of A1 (Monitor
= A1 × (Sin
When A1 ≠ A2, the monitor signal magnitude varies between
A1 and A2 at twice the rate of shaft rotation. The monitor signal
is used as described in the following sections to detect
degradation or loss of input signals.
Loss of Signal Detection
Loss of signal (LOS) is detected when either resolver input (Sin
or Cos) falls below the specified LOS Sin/Cos threshold by
comparing the monitor signal to a fixed minimum value. LOS is
indicated by both DOS and LOT latching as logic low outputs.
The DOS and LOT pins are reset to the no fault state by a rising
edge of SAMPLE . The LOS condition has priority over both the
DOS and LOT conditions, as shown in Table 4. LOS is indicated
within 45° of angular output error worst case.
Monitor
2
θ + Cos
=
2
A
θ ) = A1), independent of shaft angle.
1
×
Sin
Equation 4.
θ
x
Sin
φ
+
A
2
×
Cos
θ
×
AD2S1200
Cos
φ

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