LTC1090CSW Linear Technology, LTC1090CSW Datasheet - Page 18

• Manufacturer Part Number: LTC1090CSW
• Description: IC DATA ACQUIS SYS 10BIT 20-SOIC
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1090CSW

• Resolution (bits): 10 b
• Sampling Rate (per Second): 30k
• Data Interface: Serial
• Voltage Supply Source: Dual ±
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1090
6. Sharing the Serial Interface
The LTC1090 can share the same 3-wire serial interface
with other peripheral components or other LTC1090s (see
Figure 5). In this case, the CS signals decide which
LTC1090 is being addressed by the MPU.
ANALOG CONSIDERATIONS
1. Grounding
The LTC1090 should be used with an analog ground plane
and single point grounding techniques.
Pin 11 (AGND) should be tied directly to this ground plane.
Pin 10 (DGND) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
Pin 20 (V
a 4.7µF tantalum with leads as short as possible. Pin 12
(V
single supply applications, V
plane.
It is also recommended that pin 13 (REF
be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Figure 6 shows an example of an ideal ground plane design
for a two sided board. Of course this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
2. Bypassing
For good performance, V
ripple. Any changes in the V
analog ground during a conversion cycle can induce
errors or noise in the output code. V
be kept below 1mV by bypassing the V
analog ground plane with a 4.7µF tantalum with leads as
short as possible. Figures 7 and 8 show the effects of good
and poor V
18
–
) should be bypassed with a 0.1µF ceramic disk. For
CC
CC
) should be bypassed to the ground plane with
bypassing.
U
U
CC
–
must be free of noise and
CC
can be tied to the ground
voltage with respect to
CC
W
noise and ripple can
CC
–
) and pin 9 (COM)
pin directly to the
U
Figure 8. Good V
on V
Figure 6. Example Ground Plane for the LTC1090
CC
Figure 7. Poor V
can Cause A/D Errors
GROUND
ANALOG
PLANE
Below 1mV
4.7µF TANTALUM
CC
1
10
Bypassing Keeps Noise and Ripple
HORIZONTAL: 10µs/DIV
HORIZONTAL: 10µs/DIV
CC
Bypassing. Noise and Ripple
20
11
V
CC
0.1µF CERAMIC DISK
V –
LTC1090 • AI15
1090fc