X9116WS8Z-2.7 Intersil, X9116WS8Z-2.7 Datasheet - Page 8

• Manufacturer Part Number: X9116WS8Z-2.7
• Description: IC XDCP 16-TAP 10K CMOS 8-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9116WS8Z-2.7

• Taps: 16
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: Up/Down (3-Wire)
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 2, 11/10
1
INDEX
AREA
2
5.00 (0.197)
4.80 (0.189)
SIDE VIEW “A
0.51(0.020)
0.33(0.013)
TOP VIEW
1.27 (0.050)
8
3
1.75 (0.069)
1.35 (0.053)
4.00 (0.157)
3.80 (0.150)
-C-
SEATING PLANE
6.20 (0.244)
5.80 (0.228)
0.25(0.010)
0.10(0.004)
X9116
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
3. Package width does not include interlead flash or protrusions. Interlead
4. The chamfer on the body is optional. If it is not present, a visual index fea-
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the seat-
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
ture must be located within the crosshatched area.
ing plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
necessarily exact.
DETAIL "A"
8°
0°
1
2
3
4
TYPICAL RECOMMENDED LAND PATTERN
SIDE VIEW “B”
1.27 (0.050)
0.40 (0.016)
0.200
0.50 (0.20)
0.25 (0.01)
0.25 (0.010)
0.19 (0.008)
2.41 (0.095)
x 45°
6
5
7
8
February 3, 2011
1.27 (0.050)
0.76 (0.030)
FN8160.3