X9259US24Z-2.7 Intersil, X9259US24Z-2.7 Datasheet - Page 7

• Manufacturer Part Number: X9259US24Z-2.7
• Description: IC XDCP QUAD 256TAP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9259US24Z-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Identification Byte
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a
Device Type Identifier, ID[3:0] bits, which must be 0101.
Refer to Table 3.
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction.
The A3 - A0 inputs can be actively driven by CMOS input
signals or tied to V
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA
bits point to one of the four data registers of each associated
XDCP. The least two significant bits point to one of four
Wiper Counter Registers or DCPs. The format is shown in
Table 4.
SDA OUTPUT FROM
SDA OUTPUT FROM
SDA
SCL
TRANSMITTER
SCL FROM
RECEIVER
CC
MASTER
or V
START
SS
.
7
START
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
STABLE
DATA
1
CHANGE
DATA
X9259
STABLE
DATA
Data Register Selection
#: 0, 1, 2, or 3
The least significant four bits of the Identification Byte are
the Slave Address bits, AD[3:0]. To access the X9259, these
four bits must match the logic values of pins A3, A2, A1, and
A0.
REGISTER
DR#0
DR#1
DR#2
DR#3
8
STOP
ACK
9
RB
0
0
1
1
April 13, 2007
RA
0
1
0
1
FN8169.5