X9250US24Z-2.7 Intersil, X9250US24Z-2.7 Datasheet
X9250US24Z-2.7
Specifications of X9250US24Z-2.7
Available stocks
Related parts for X9250US24Z-2.7
X9250US24Z-2.7 Summary of contents
Page 1
... L1 L1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9250 FN8165.3 ...
Page 2
... X9250TS24Z-2.7 (Note) X9250TS ZF X9250TS24I-2.7* X9250TS G X9250TS24IZ-2.7* X9250TS ZG (Note) X9250TV24I-2.7 X9250TV G X9250TV24IZ-2.7 (Note) X9250TV ZG X9250US24-2.7* X9250US F X9250US24Z-2.7* (Note) X9250US ZF X9250US24I-2.7 X9250US G X9250US24IZ-2.7 (Note) X9250US ZG X9250UV24-2.7 X9250UV F X9250UV24Z-2.7 (Note) X9250UV ZF X9250UV24I-2.7 X9250UV G X9250UV24IZ-2.7 (Note) X9250UV ZG *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
Page 3
PIN DESCRIPTIONS Serial Output (SO serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the ...
Page 4
DEVICE DESCRIPTION Serial Interface The X9250 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be ...
Page 5
Figure 1. Detailed Potentiometer Block Diagram (One of Four Arrays) Serial Data Path From Interface Circuitry Register 0 Register 2 If WCR = 00[H] then WCR = FF[H] then V ...
Page 6
The four high order bits of the instruction byte specify the operation. The next two bits (R one of the four registers that acted upon when a register oriented instruction is issued. The last two bits (P1 ...
Page 7
Figure 4. Two-Byte Instruction Sequence CS SCK Figure 5. Three-Byte Instruction Sequence (Write) CS SCL Figure 6. Three-Byte Instruction Sequence (Read) CS SCL ...
Page 8
Figure 8. Increment/Decrement Timing Limits SCK INC/DEC CMD Issued Table 1. Instruction Set Instruction I 3 Read Wiper Counter 1 Register Write Wiper Counter 1 Register Read Data Register 1 Write Data Register 1 XFR ...
Page 9
Instruction Format Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK ...
Page 10
Transfer Wiper Counter Register (WCR) to Data Register (DR) device type device CS identifier addresses Falling A A Edge Increment/Decrement Wiper Counter Register (WCR) device type device CS identifier addresses Falling A ...
Page 11
ABSOLUTE MAXIMUM RATINGS Temperature under bias ........................ -65 to +135°C Storage temperature ............................. -65 to +150°C Voltage on SCK, SCL or any address input with respect to V ................................. -1V to +7V SS Voltage on V+ (referenced ...
Page 12
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter I V supply current CC1 CC (active supply current CC2 CC (nonvolatile write current (standby Input leakage current LI I ...
Page 13
Circuit #3 SPICE Macro Model R TOTAL 10pF 25pF TIMING Symbol f SSI/SPI clock frequency SCK t SSI/SPI clock cycle time CYC t SSI/SPI clock high time WH t SSI/SPI clock ...
Page 14
HIGH-VOLTAGE WRITE CYCLE TIMING Symbol t High-voltage write cycle time (store instructions) WR XDCP TIMING Symbol t Wiper response time after the third (last) power supply is stable WRPO t Wiper response time after instruction issued (all load instructions) WRL ...
Page 15
Output Timing CS SCK t V MSB SO ADDR SI Hold Timing CS SCK HOLD XDCP Timing (for all Load Instructions) CS SCK MSB SI VWx High Impedance SO 15 X9250 ... t HO ... t ...
Page 16
XDCP Timing (for Increment/Decrement Instruction) CS SCK VWx SI ADDR High Impedance SO Write Protect and Device Address Pins Timing X9250 ... t WRID ... ... Inc/Dec Inc/Dec (Any Instruction WPAH WPASU FN8165.3 ...
Page 17
APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers V R Three terminal Potentiometer; Variable voltage divider Application Circuits Noninverting Amplifier – (1 Offset Voltage Adjustment R ...
Page 18
Application Circuits (continued) Attenuator – -1/2 ≤ G ≤ +1/2 Inverting Amplifier – + ...
Page 19
Thin Shrink Small Outline Package Family (TSSOP (N/2)+ (N/2) B TOP VIEW e C SEATING PLANE b 0.10 0. LEADS SIDE VIEW SEE DETAIL “X” c END VIEW ...
Page 20
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...