BU2507FV-E2 Rohm Semiconductor, BU2507FV-E2 Datasheet - Page 5

• Manufacturer Part Number: BU2507FV-E2
• Description: IC DAC 10BIT 6-CHAN SSOP-B14
• Manufacturer: Rohm Semiconductor

Specifications of BU2507FV-E2

• Data Interface: Serial
• Settling Time: 7µs
• Number Of Bits: 10
• Number Of Converters: 6
• Voltage Supply Source: Single Supply
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SSOP
• Resolution (bits): 10bit
• Sampling Rate: 10MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Current: 850µA
• Digital Ic Case Style: SSOP
• No. Of: RoHS Compliant
• Resolution: 10 bit
• Interface Type: Serial (3-Wire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 30 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: BU2507FV-E2; BU2507FV-E2TR

●Command Sending
© 2009 ROHM Co., Ltd. All rights reserved.
BU2508FV,BU2507FV
www.rohm.com
DACOUT
D 13
D 13
DACOUT
1) In the case of BU2507FV
2) In the case of BU2508FV
CLK
(1) Data format [data : LSB first]
(2) Data timing diagram
DI
LD
D13
(2) Data timing diagram
D13
CLK
DI
LD
：
：
(1) Data format [Data: LSB first ]
0
0
0
0
1
1
0
0
0
0
1
1
D 12
D 12
D 11
D 11
D12
D12
ADDRESS
ADDRESS
：
：
0
0
0
0
1
1
D /A converter output setting DATA
0
0
0
0
1
1
D /A converter output setting DATA
LSB
LSB
D 0
D 0
D 10
D10
D1
D1
D 9
D11
D11
D9
：
：
0
0
0
0
1
1
0
0
0
0
1
1
D 2
D 2
ADDRESS
D 8
ADDRESS
D 8
MSB
MSB
D 3
D 3
D10
D10
：
：
D7
0
0
0
0
1
1
0
0
0
0
1
1
D7
DATA
DATA
LSB
LSB
D 4
D 4
D6
D 6
D9
D9
：
：
0
0
0
0
1
1
0
0
0
0
1
1
D 5
D 5
D 11
D 11
D 4
D 4
D 12
D 12
D8
D8
：
：
0
0
0
0
1
1
0
0
0
0
1
1
D3
DATA
D3
MSB
D13
DATA
D13
MSB
address select
address select
D2
D7
D7
：
：
D2
0
0
0
0
1
1
0
0
0
0
1
1
D1
5/8
D1
D6
D6
：
：
0
0
0
0
0
1
1
D0
0
0
0
1
1
D0
D5
D5
：
：
0
0
1
1
1
1
0
0
1
1
1
1
D3
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D4
D4
：
：
0
1
0
1
0
1
0
1
0
1
0
1
D2
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D/A output (VrefH=VDD, VrefL=VSS)
VrefL
(VrefH-VrefL)/1024×1+VrefL
(VrefH-VrefL)/1024×2+VrefL
(VrefH-VrefL)/1024×3+VrefL
(VrefH-VrefL)/1024×1022+VrefL
(VrefH-VrefL)/1024×1023+VrefL
VrefL
(VrefH-VrefL)/1024×1+VrefL
(VrefH-VrefL)/1024×2+VrefL
(VrefH-VrefL)/1024×3+VrefL
(VrefH-VrefL)/1024×1022+VrefL
(VrefH-VrefL)/1024×1023+VrefL
D/A output (VrefH=VDD, VrefL=VSS)
D1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Technical Note
:
:
Address selection
Address selection
2011.04 - Rev.B
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
AO1 selection
AO2 selection
AO3 selection
AO4 selection
AO5 selection
AO6 selection
AO1 selection
AO2 selection
AO3 selection
AO4 selection
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care