CS43L21-CNZ Cirrus Logic Inc, CS43L21-CNZ Datasheet - Page 31

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CS43L21-CNZ

Manufacturer Part Number
CS43L21-CNZ
Description
IC DAC 24BIT 98DB 96KHZ 32QFN
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS43L21-CNZ

Package / Case
32-QFN
Number Of Bits
24
Data Interface
Serial
Number Of Converters
2
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
96 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
1.8 V or 2.5 V
Operating Temperature Range
+ 70 C
Mounting Style
SMD/SMT
Number Of Dac Outputs
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1282 - BOARD EVAL FOR CS43L21 DAC
Power Dissipation (max)
-
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1187

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DS723A1
4.6
4.7
LRCK
SCLK
LRCK
SCLK
SDIN
SDIN
Initialization
The initialization and Power-Down sequence flowchart is shown in
ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu-
lators and control port registers are reset. The internal voltage reference, multi-bit DAC and switched-
capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in
10 ms, the will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, FILT+ will begin pow-
ering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in
6. Set the PDN bit to ‘0’b.
7. Apply LRCKSCLK and SDIN for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
M S B
“Software Mode” on page
by”.
prevent power glitch related issues.
AOUTA / AINxA
L eft C h a n n e l
AOUTA
L eft C h a n n el
M S B
Figure 16. Right-Justified Format (DAC only)
33. If a valid write sequence to the control port is not made within approximately
Figure 15. Left-Justified Format
L S B
L S B
M S B
Section
AOUTB / AINxB
R ig ht C h a n n e l
Figure 17 on page
4.4.
R ig ht C h a n n el
AOUTB
M S B
32. The CODEC en-
L S B
CS43L21
MSB
L S B
31

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