CS43L21-CNZ Cirrus Logic Inc, CS43L21-CNZ Datasheet - Page 41

• Manufacturer Part Number: CS43L21-CNZ
• Description: IC DAC 24BIT 98DB 96KHZ 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L21-CNZ

• Package / Case: 32-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 70 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1282 - BOARD EVAL FOR CS43L21 DAC
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1187

DS723A1
6.4
6.5
HP_GAIN2
Reserved
7
7
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
Interface Control (Address 04h)
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
Function:
Selects either master or slave operation for the serial port.
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
Function:
Selects the digital interface format used for the data in on SDIN. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are
detailed in the section
DAC Output Control (Address 08h)
Headphone Analog Gain (HP_GAIN[2:0])
Default: 011
HP_GAIN[2:0]
DAC_DIF[2:0]
000
001
010
011
100
101
110
111
HP_GAIN1
000
001
010
100
101
100
011
110
M/S
6
6
Gain Setting
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Right-Justified, 16-bit data
Reserved
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Reserved
“Digital Interface Formats” on page
HP_GAIN0
DAC_DIF2
0.3959
0.4571
0.6047
0.7099
0.8399
1.0000
1.1430
0.5111
5
5
Description
DAC_DIF1
SNGVOL
DAC_
4
4
INV_PCMB
DAC_DIF0
3
3
30.
17 on page 3217 on page 32
17 on page 3217 on page 32
17 on page 3217 on page 32
17 on page 3217 on page 32
INV_PCMA
Reserved
2
2
15 on page 31
14 on page 30
Figure
-
-
DACB_MUTE DACA_MUTE
Reserved
1
1
CS43L21
Reserved
0
0
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