CS4353-CZZ Cirrus Logic Inc, CS4353-CZZ Datasheet - Page 16

• Manufacturer Part Number: CS4353-CZZ
• Description: IC DAC STER 106DB 2VRMS 24-QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS4353-CZZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 152mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1519 - BOARD EVAL FOR CS4353 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16
4.6
4.7
De-emphasis Control
The device includes on-chip digital de-emphasis.
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs.
The de-emphasis error will increase for sample rates other than 44.1 kHz.
When the DEM pin is connected to VL, the 44.1 kHz de-emphasis filter is activated. When the DEM pin is
connected to GND, the de-emphasis filter is turned off.
Note:
Internal Power-on Reset
The CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be
connected to VL during power-up and power-down sequences if the external reset function is not needed.
This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s
digital circuitry when the supply reaches defined thresholds (see
ages” on page
When power is first applied, the POR circuit monitors the VCP supply voltage to determine when it reaches
a defined threshold, V
digital circuitry. Once the VCP supply reaches the secondary threshold, V
internal reset.
Note:
When power is removed and the VCP voltage reaches a defined threshold, V
internal reset low, resetting all of the digital circuitry.
De-emphasis is only available in Single-Speed Mode.
For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-
neously with VCP.
(external)
10). No external clocks are required for the POR circuit to function.
RESET
DGND
VCP
on1
-10dB
. At this time, the POR circuit asserts the internal reset low, resetting all of the
Gain
Figure 8. Internal Power-on Reset Circuit
0dB
dB
Figure 7. De-emphasis Curve, Fs = 44.1 kHz
Power-On Reset
3.183 kHz
T1=50 µs
Circuit
F1
Figure 7
10.61 kHz
F2
shows the de-emphasis curve for Fs equal to
T2 = 15 µs
Frequency
“Internal Power-on Reset Threshold Volt-
on2
off
(internal)
, the POR circuit releases the
reset
, the POR circuit asserts the
CS4353
DS803F1