CY8C5246AXI-054 Cypress Semiconductor Corp, CY8C5246AXI-054 Datasheet - Page 26

• Manufacturer Part Number: CY8C5246AXI-054
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-054

• Lead Free Status / Rohs Status: Compliant

6.3 Reset
CY8C52 has multiple internal and external reset sources
available. The reset sources are:
Figure 6-7. Resets
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
Document Number: 001-55034 Rev. *F
Reset
Pin
Power source monitoring - The analog and digital power
voltages, V
different modes during power up, active mode, and sleep mode
(buzzing). If any of the voltages goes outside predetermined
ranges then a reset is generated. The monitors are program-
mable to generate an interrupt to the processor under certain
conditions before reaching the reset thresholds.
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull up to Vddio1. V
have voltage applied before the part comes out of reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software - The device can be reset under program control.
IPOR - Initial Power on Reset
At initial power on, IPOR monitors the power voltages V
and V
DDA
Vddd Vdda
Watchdog
, both directly at the pins and at the outputs of the
Monitors
Software
External
Register
Voltage
DDA
Power
Reset
Timer
Reset
Level
, V
DDD
, Vcca, and Vccd are monitored in several
DDD
Controller
, V
Reset
DDA
, and Vddio1 must all
PRELIMINARY
System
Processor
Reset
Interrupt
DDD
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
6.3.1.2 Other Reset Sources
Interrupt Supply
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest spec-
ified operating voltage but high enough for the internal circuits
to be reset and to hold their reset state. The monitor generates
a reset pulse that is at least 100 ns wide. It may be much wider
if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. Voltage supervision is then handed off
to the precise low voltage reset (PRES) circuit. When the volt-
age is high enough for PRES to release, the IMO starts.
PRES - Precise Low Voltage Reset
This circuit monitors the outputs of the analog and digital inter-
nal regulators after power up. The regulator outputs are com-
pared to a precise reference voltage. The response to a PRES
trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the dig-
ital PRES circuit. The analog regulator can be disabled, which
also disables the analog portion of the PRES. The PRES cir-
cuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory ser-
vices and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
Interrupt circuits are available to detect when V
go outside a voltage range. For AHVI, V
fixed trip level. For ALVI and DLVI, V
pared to trip levels that are programmable, as listed in
Table
a device reset instead of an interrupt.
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be ser-
viced.
XRES - External Reset
CY8C52 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
AHVI
DLVI
ALVI
PSoC
6-5. ALVI and DLVI can also be configured to generate
®
V
V
V
DDD
DDA
DDA
5: CY8C52 Family Data Sheet
1.71 V-5.5 V 1.70 V-5.45 V in
1.71 V-5.5 V 1.70 V-5.45 V in
1.71 V-5.5 V 5.75 V
Normal
Voltage
Range
250 mV
increments
250 mV
increments
Available Trip
Settings
DDA
DDA
and V
is compared to a
DDA
DDD
Accuracy
Page 26 of 88
and V
are com-
±2%
±2%
±2%
DDD
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