TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 11

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

CUBIT- Pro CELL INLET AND OUTLET PORTS
The Cell Inlet and Outlet ports constitute the main interfaces for the cell traffic between the CUBIT- Pro and
other devices in either the upper ATM or Physical (PHY) Layers. Several interfaces are supported by the
device: UTOPIA 8-bit mode, TranSwitch 16-Bit mode, TranSwitch ALI-25 device interface mode, and Back-to-
Back (CUBIT- Pro -to-CUBIT- Pro interface).
The CUBIT- Pro can provide address translation if selected via the input pin TRAN (pin 154). If no translation is
selected, the external hardware must provide the CellBus Bus Routing Header, the Tandem Routing Header
(optional), and the ATM cell. If translation mode is selected, the hardware is required only to provide the ATM
cell and the CUBIT- Pro will perform the translation based on the information programmed into the attached
translation SRAM.
For all the modes the cell size is selectable via external pins LMODE2, LMODE1 and LMODE0 (pins 156, 157,
and 158, respectively), as described below. This feature permits the CUBIT- Pro to accommodate the require-
ments for different designs.
Additionally, the UTOPIA and 16-Bit modes can be selected to behave as either the master (ATM layer device)
or the slave (PHY layer device). The selection between ATM and PHY layer device for the UTOPIA and 16-Bit
modes is made via the PHYEN pin (pin 48), where a low enables PHY layer device operation.
The CUBIT- Pro allows the selection of the clock for the cell Inlet/Outlet operation from three different sources:
CellBus bus clocks (CBRC, pin 78 and CBWC, pin 77), processor clock (PCLK, pin 32), or an externally
supplied clock (LCLOCK, pin 45). The clock selected will be used for the UTOPIA and 16-Bit ATM layer device
modes, the ALI-25 (cell inlet clock) mode, and the Back-to-Back (cell inlet clock) mode, for which the CUBIT-
Pro sources the interface clock. For all other modes the clock is an input to the CUBIT- Pro . The selection of
the clock source for the cell interfaces is performed via two control bits in register 0BH: CLKS1, CLKS0. The
coding for the clock selection is as follows:
8-Bit UTOPIA Mode - ATM and PHY Layer Emulation
Typical signal connections for the CUBIT- Pro when operating in UTOPIA mode are illustrated in Figures 6 and
7, for ATM Layer and PHY Layer cell level handshake modes, respectively. The operating mode options for
UTOPIA mode are controlled by the input pins TRAN, PHYEN, LMODE2, LMODE1 and LMODE0, as indicated
in the tables of Figures 6 and 7. TRAN selects the internal translation mode, if asserted. In UTOPIA mode,
PHYEN determines whether the CUBIT- Pro emulates an ATM or PHY device. LMODE2, LMODE1 and
LMODE0 determine the cell inlet/outlet cell size.
When internal translation is used, the cell I/O is exactly that defined by UTOPIA, with 53-byte inlet cells. For
applications in which the internal translation function is not used, the timing and logical flow of the cell I/O is still
identical to that of UTOPIA, except that 57-byte or 55-byte inlet cells are used, instead of 53. The additional
bytes are the Routing Header bytes which would be inserted by the CUBIT- Pro if the translation function were
used, but are instead added by an external translation function. The pin connections and the different inlet and
outlet byte counts per cell in the various modes are shown in the table of Figure 6 for ATM Layer emulation.
Similarly, Figure 7 shows the pin connections and byte counts for PHY Layer emulation.
The ABRENA pin must be held high or left floating (it has internal pull-up) for proper UTOPIA mode operation.
CLKS1, CLKS0 = 0,0: Cell interface clock = CellBus bus clock divided by 2
CLKS1, CLKS0 = 0,1: Cell interface clock = LCLOCK clock divided by 2
CLKS1, CLKS0 = 1,0: Cell interface clock = PCLK clock divided by 2
CLKS1, CLKS0 = 1,1: Reserved, do not use
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LINEDIV
LINEDIV
LINEDIV
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB