TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 20

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

Forward Explicit Congestion Notification (FECN)
The CUBIT- Pro can notify an impending congested state by setting to one the middle bit of the Payload Type
(PT) field in the ATM cell header. This Explicit Forward Congestion Indication bit (EFCI) will be asserted on a
cell if both of two conditions occur at the same time:
The activation of the EFCI bit in the single-queue (QM = 0) and split-queue (QM = 1) modes is illustrated in Fig-
ures 15 and 16, respectively.
Figure 15 shows a starting condition for the single-queue mode soon after the congestion conditions a) and b)
have both become present, with three cells in the queue when VBRLIMIT is set to 2. Cells #1, #2 and #3
reached the Sync FIFO before the congestion occurred, so they are not marked with a congestion indication
and have a PT value of X0X. The first cell in the queue (cell #4) is marked with a congestion indication (PT =
X1X) and it moves into the Sync FIFO when the outlet link is free and Cell #1 is sent to the cell outlet port. Cells
#5 and #6 then shift to the left, putting Cell #6 at the VBRLIMIT = 2 boundary, so congestion persists and Cell
# 5 is also marked with PT = X1X. When this cell moves into the Sync FIFO, Cell #6 shifts left and it is the only
cell left in the queue, assuming no more cells have joined the queue. Since the queue length of 1 is now less
than VBRLIMIT = 2, condition b) no longer exists and cell #6 carries no congestion marking (PT = X0X).
a) Bit 0 in register 0CH is set to one (IFECN = 1), and
b) QM (bit 2 in register 0CH) = 0 and VBR Limit reached, or QM=1 and VBR Limit or CBR Limit reached.
Outlet
Note: The IFECN control bit is set to 1. The EFCI congestion indication is the middle bit of the PT sequence
Port
Cell
(X0X or X1X). Its value is determined when the cell leaves the queue.
Figure 15. Example of Congestion Indication in Single-Queue Mode (QM = 0)
X0X
Cell
#1
Sync FIFO
X0X
Cell
#2
X0X
Cell
#3
- 20 -
X1X
Cell
#4
VBRLIMIT = 2
X1X
Cell
#5
X0X
Cell
#6
Single Queue
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB