PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 15

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1.3
Pin No.
P-LCC
23
24
25
2
26
27
29
30
31
32
33
34
22
Semiconductor Group
Pin Definitions and Functions (cont’d)
Symbol
CS
V
RD
WR
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
DD
Input (I)
Output (O)
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Address Data Bus: If the multiplexed
address/data P-interface bus mode is selected
these pins transfer data and addresses between
the P and the MUSAC-A.
If a demultiplexed mode is used, these bits inter-
face with the system data bus.
Chip Select: A low level selects the MUSAC-A for
a register access operation.
Supply Voltage: 5 V
Read: This signal indicates a read operation and is
internally sampled only if CS is active. The
MUSAC-A puts data from the selected internal reg-
ister on the data bus with the falling edge of RD.
RD is active low (Siemens/Intel bus mode).
Write: This signal initiates a write operation. The
WR input is internally sampled only if CS is active.
In this case the MUSAC-A loads an internal regis-
ter with data from the data bus at the rising edge of
WR. WR is active low (Siemens/Intel bus mode).
Address Latch Enable: In the Intel type multi-
plexed
cates an address of a MUSAC-A internal register
on the external address/data bus. In the Intel type
demultiplexed.
the demultiplexed Motorola type P-interface
mode it should be connected to
If ALE is not connected it will be set to ground inter-
nally.
P-interface mode a logical high on this line indi-
P-interface mode this line is hardwired to
15
5 %
V
DD
.
PEB 2445
Overview
V
SS
02.96
, in