PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 41

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1
2
3
If A1 is not connected it is internally set to ground. In the demultiplexed mode neither an
access to the CMR, CST nor a read access to the MOD register is possible.
The paragraphs in this section cover the registers in detail.
4.1
Access in the multiplexed P-interface mode:
RI
SB
MI1/0
4
The following registers may be accessed:
Table 6
Addressing the Direct Registers
Demultiplexed Mode
A(1:0)
0
Access in the demultiplexed P-interface mode: Write, address: 0
Reset value: BF
RC
MO1/0
Semiconductor Group
H
H
H
H
Detailed Register Description
Mode Register (MOD)
AD7
Reset Connection memory; writing a zero to this bit causes the complete
STA:B is set. The maximum time for resetting is 250 s.
connection memory to be overwritten with 200
Reset Indirect access mechanism; setting this bit resets the indirect access
mechanism. Rl has to be cleared before writing/reading IAR after reset.
Stand By; By selecting SB = 1 all PCM outputs are tristated. The connection
memory works normally. The MUSAC-A can be activated immediately by
resetting SB.
Input/Output operation Mode; these bits define the bit rate of the input and
output lines. The bitrates are given in table 7, the corresponding pin functions
in table 8 (standard configuration).
RC
H
Address
0
Multiplexed Mode
AD(7:0)
0
2
4
6
H
H
H
H
RI
SB
41
Write Operation
MOD
IAR
CMR
–
MI1
Write, address: 0
MI0
Detailed Register Description
H
(tristate). During this time
MO1
Read Operation
H
H
STA
IAR
CST
MOD
read, address: 6
read, address: 0
AD0
MO0
PEB 2445
02.96
H
H