PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 139

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Lantiq

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

Figure 48
If a Txd and CxD difference occur, the HDLC aborts its transmission, generates an
interrupt for the DSP reporting the collision and disables the output of TxD (High
Impedance or ‘1’ programmable selecting). The HDLC automatically restarts
transmission when the bus is detected to be idle again. The HDLC detects idle if CxD
was ‘high’ for (8 + 2*Class + D), where Class is a DSP programmable and is 0 for class
1 and 1 for class 2. D is 1 between a success transmission and idle detection on the bus.
4.7.4
The memory in the GHDLC is build by a 128 x 8 bit RAM equally divided between the
GHDLC and the DSP. The GHDLC has a receive buffer and a transmit buffer, divided
into two blocks. One block is allocated to the GHDLC channel in the receive direction,
the other block is read by the DSP. Similarly in the transmit buffer, one block is allocated
to the GHDLC channel in the transmit direction, the other block is written to by the DSP
as shown in
whereas the DSP is able to read and write the RAM at a much higher frequency.
The DELIC contains 4 GDLC Controllers.
If only one GHDLC Controller is used, the visible buffer size is 32 bytes for each
direction, for two channels 16 bytes per channel and for 4 channels 8 bytes per channel.
Memory is allocated to each receive and transmit buffer according to the number of used
channels by the following table:
Data Sheet
GHDLC Memory Allocation
Figure
Point-to-Multi Point Bus Structure
49. Note that the GHDLC has higher priority for the buffer access,
DSP
HDLC
TxD
CxD
RxD
TxD
CxD
RxD
TxD
CxD
RxD
122
Group Controller
Functional Description
PEB 20570
PEB 20571
2003-07-31