PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 34

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Lantiq

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

Table 4
Pin
No.
14
15
7
6
5
29
89
Data Sheet
Symbol In (I)
RD/
DS
ALE
MODE
IREQ
IACK
RESET
RESIND O
Microprocessor Bus Interface Pins (DELIC-LC) (cont’d)
Out (O)
I
I
I
O
(OD)
I
I
During
Reset
I
I
I
High Z
(OD)
I
I
O
After
Reset
I
I
I
High Z
(OD)
I
I
O
17
Function
Read (Intel/Infineon Mode)
Indicates a read access.
Data Strobe (Motorola Mode)
During a read cycle, DS indicates that
the DELIC should place valid data on
the bus. During a write access, DS
indicates that valid data is on the bus.
Address Latch Enable
Controls the on-chip address latch in
multiplexed bus mode. While ALE is
’high’, the latch is transparent. The
falling edge latches the current
address. ALE is also evaluated to
determine the bus mode
(’low’=multiplexed,
’high’=demultiplexed)
Bus Mode Selection
Selects the µP bus mode
(’low’=Intel/Infineon, ’high’=Motorola)
Interrupt Request is programmable to
push/pull (active high or low) or open-
drain. This signal is activated when the
DELIC requests a µP interrupt. When
operated in open drain mode, multiple
interrupt sources may be connected.
Interrupt Acknowledge
System Reset
DELIC is forced to go into reset state.
Reset Indication
Indicates that the DELIC is executing a
reset. The DELIC remains in reset state
for at least 500 µs after the termination
of the RESET pulse.
Pin Description
PEB 20570
PEB 20571
2003-07-31