PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 151

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

DMA mode, and the data transfer direction.
Two DMA modes are supported:
• Two-cycle DMA transfer mode called also Memory-to-memory mode
• Single cycle DMA transfer mode called also Fly-by mode
An example for a two-cycle DMA transfer in receive direction (data is read from DELIC
and written to memory) in Intel/Infineon Mode is shown in
Figure 52
1. The DMA mailbox contains data (the receive mailbox contains up to 16 bytes of data)
2. DELIC requests DMA service via DREQR
3. DMA controller issuses a DMA Acknowledge (DACK) signal for addressing the DMA
4. The DMA controller reads the data into an on-chip register (= end of first cycle).
5. The DMA controller writes the data into the memory using ADDR and WR (= second
The main advantage of the two-cycle DMA transfer mode, compared to general mailbox
access by a P, is its faster response time (depends on the operating system) and a
simple data flow control.
Data Sheet
mailbox and a "read" signal for indicating DELIC that it will read the receive mailbox
cycle).
2-Cycle-Mode
Controller
DMA
1. cycle
Two-cycle DMA Transfer Mode for Receive Direction
DREQR
DACK
+ RD
Memory
Mailbox
DELIC
DMA
Data
Data
Bus
134
Controller
DMA
2. cycle
Figure
WR
Functional Description
ADDR
52.
Memory
Mailbox
DELIC
DMA
PEB 20570
PEB 20571
Data
2003-07-31
Data
Bus