PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 91

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

4.2.4.4
The operational mode command and status bits usually are served completely by the
firmware. So there is no need to set this bits by the user.
Operational Mode Command bits in the data RAM:
Address:see memory map
WR_ST
MSYNC
SMINI(2:0)
Data Sheet
7
x
Command and Status format in the Data RAM
6
x
Write Command to TST1 Bits (S/T, U
0 = Data sent in these bits is invalid
1 = SMINI(2:0) and MSYNC contain valid data
Multiframe Synchronization (LT-T)
0 = VIP mirrors the F
1 = VIP stops the F
State Machine Initialization (S/T, U
Command to VIP from the DELIC layer-1 state machine. Depending
on the state, the VIP may transmit data on the U
The VIP responds by sending the receiver status bits
STAT_n_m.RxSTA(1:0) to the DELIC.
000 = INFO 0 in S/T or U
001 = INFO 1w in U
010 = INFO 1 in LT-T, INFO 2 in LT-S or U
011 = INFO 3 in LT-T, INFO 4 in LT-S or U
100 = Test mode ’Send Continuous Pulses SCP’:
101 = Test mode ’Send Single Pulses SSP’ (at 2 kHz burst rate)
all other states are reserved
’1s’ transmitted at 96 kHz (U
5
x
4
A
data byte 1
data byte 2
data byte 3
PN
-bit mirroring (for multiframe synchronization)
A
SMINI(2:0)
-bit
74
PN
3
PN
) and at 192 kHz S/T)
PN
PN
)
2
)
PN
PN
Functional Description
MSYNC
PN
1
or S/T interface.
PEB 20570
PEB 20571
WR_ST
2003-07-31
0