PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 161

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

4.11.2
The default DSP clock is the internal 61.44 MHz generated by the PLL. For test purpose,
a different frequency may be provided via DSP_CLK input pin. The selection between
the internal 61.44 MHz or external clock source is done by the DSP_FRQ input pin.
4.11.3
In PCM Master mode, the PFS and PDC are derived from the internal 16.384 MHz
signal, and driven to the PCM interface via the PFS pin (output) and PDC pin (output).
In PCM Slave mode, the PFS and PDC are generated from an external signal, and input
to the DELIC via the PFS pin and the PDC pin.
Note: During reset, a strap pin determines whether the DELIC operates in clock Master
4.11.4
The PCM clock division chain is synchronized to an external reference clock, used as
one of the inputs to a phase comparator, after being divided into 8 KHz. The other phase
comparator input is the 8 KHz clock, derived from the 16.384 MHz clock. The phase
comparator output is used as control input of the DCXO, after being filtered by a low-pass
filter. The reference clock can be driven by one of the following input pins:
• XCLK - 2.048 MHz, 1.536 MHz or 8 KHz:
• REFCLK - 512 KHz or 8 KHz:
• PFS - 8 KHz:
4.11.5
The IOM-2 interface clocks FSC and DCL are always output.
The FSC output signal is usually generated with 50% duty cycle. A short FSC pulse is
required for multiframe start indication (one DCL cycle long). One cycle after the short
FSC pulse, the normal FSC is generated again with 50% duty cycle.
Data Sheet
Can be driven by a layer-1 transceiver (e.g. VIP, QUAT-S) connected to the Central
Office. Only a clock master DELIC can be synchronized directly according to this
input. In other cases (clock slave DELIC), this input signal may be divided to 8 KHz or
512 KHz, and driven out via REFCLK, in purpose to be used for the synchronization
of the clock-master DELIC.
Used for synchronization of the clock master DELIC, when not synchronized by XCLK.
Usually this signal is driven by a clock slave DELIC, or another PBX in the system. In
a clock slave DELIC this pin is used as output.
Driven by the system clock master. May be used for synchronization of the clock slave
DELICs. In a clock master DELIC this pin is used as output.
or Slave mode. When setting to slave mode the register PFS SYNC
(Chapter
DSP Clock Selection
PCM Master/Slave Mode Clocks Selection
DELIC Clock System Synchronization
IOM-2 Clock Selection
6.2.11.10) has to be written in order to align the clocks.
144
Functional Description
PEB 20570
PEB 20571
2003-07-31