PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 71

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

3.2.4
A finite state machine in the DELIC controls the VIP S/T line activation/deactivation
procedures and transmission of special pulse patterns. Such actions can be initiated by
primitives (INFOs) on the S/T interface or by C/I codes sent via the mailbox.
Depending on the application mode and the transfer direction, the S/T state machines
support different codes in conditional and unconditional states:
LT-S mode
Codes:
States:
The state diagram is shown in
LT-T mode
Codes
Conditional states: power up, pending deactivation, synchronized, slip detected,..
The state diagram is shown in
Unconditional states may be entered from any conditional state and should be left with
the command TIM: test mode, reset state,..
The S/T layer-1 activation and deactivation procedures implemented in the DELIC are
similar to the ones implemented in the PEB 2084, QUAT-S.
Data Sheet
S/T State Machine
data downstream = Commands: reset, test mode, activate req,..
data upstream
deactivated, activated, pending, lost framing, test mode
data upstream
data downstream = Indications: command x acknowledged,..
= Indications: not sync, code violation, timer out,..
= Commands: reset, test, activate request,..
Figure
Figure
17.
18.
54
Interface Description
PEB 20570
PEB 20571
2003-07-31