CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 12

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

7.1
Table 7-1. Operating Registers Addressing Mapping (ADR[9] = 1)
7.2
Table 7-2 shows the organization of the context descriptor.
During normal operation, the network processor Writes in the
context descriptor block (addresses 0–9 within the block) with
the command and the appropriate data and Reads the results
from the context descriptor block (addresses 12–15 within the
block). Note. In 64-bit bus mode, the even and the next odd
location are accessed in the same cycle, and ADR[0] is
ignored.
Document #: 38-02043 Rev. *C
Address Mapping
Context Descriptor Organization
ADR[8:0]
112–127
128–143
144–159
160–175
176–191
192–207
208–223
223–239
240–255
256–271
272–287
288–303
304–319
320–335
336–351
352–367
368–383
384–399
400–415
416–431
432–447
448–463
464–479
480–495
496–511
96–111
16–31
32–47
48–63
64–79
80–95
0–15
Context 10
Context 11
Context 12
Context 13
Context 14
Context 15
Context 16
Context 17
Context 18
Context 19
Context 20
Context 21
Context 22
Context 23
Context 24
Context 25
Context 26
Context 27
Context 28
Context 29
Context 30
Context 31
Contents
Context 0
Context 1
Context 2
Context 3
Context 4
Context 5
Context 6
Context 7
Context 8
Context 9
CYNCP80192
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