CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 25

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CYNCP80192-BGC

Manufacturer Part Number
CYNCP80192-BGC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYNCP80192-BGC

Lead Free Status / Rohs Status
Not Compliant

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14.0
As more NSEs are added to the DQ bus, the capacitive load
on the bus increases, reducing the bus speed. CYNSE80192
gets around this by using external transceivers, and provides
a glueless support to add the transceivers (Phillips
74ALVT16652)
CYNPC80192 (see Figure 14-1).
The XVER_0, XVER_1, and XVER_2 are electrically buffered
versions of the same logical signal in the CYNPC80192
device. The XVER_0_L, XVER_1_L, and XVER_2_L are also
electrically buffered versions of the same logical signal in the
CYNPC80192 device. Multiple copies of these signals are
Document #: 38-02043 Rev. *C
Information on External Transceivers
between
Figure 14-2. Transceiver Connected Between CYNPC80192 and CYNSE70XXX Devic-
a bank
of
Figure 14-1. Use of Transceiver Enables
NSEs
CYNCP80192
XVER_1_L
CLK (System Clock)
XVER_1
XVER_2
XVER_0_L
and
XVER_0
the
XVER_2_L
provided in order to increase the ability of the signal to drive
many transceiver devices of eight-bit width. Figure 14-2 shows
one example of the distribution of signals driving the
transceivers.
Transceivers
Transceivers
Transceivers
Transceivers
SSRAM
NSEs
CYNCP80192
Page 25 of 37

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