PSD813F2VA-15MI STMicroelectronics, PSD813F2VA-15MI Datasheet
PSD813F2VA-15MI
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PSD813F2VA-15MI Summary of contents
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Flash in-system programmable (ISP) peripherals FEATURES SUMMARY ■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS ■ DUAL BANK FLASH MEMORIES – Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8) – 256 Kbit ...
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PSD813F2V, PSD854F2V TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PSD813F2V, PSD854F2V PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MAXIMUM RATING ...
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PSD813F2V, PSD854F2V SUMMARY DESCRIPTION The PSD8XXFX family of memory systems for mi- crocontrollers (MCUs) brings In-System-Program- mability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of ...
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Figure 2. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 39 AD15 ...
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PSD813F2V, PSD854F2V Figure 3. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 8/109 Doc ID 10552 Rev 3 AD15 ...
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Figure 4. TQFP64 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 10 GND 11 PC3 12 PC2 13 PC1 14 PC0 Doc ID ...
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PSD813F2V, PSD854F2V PIN DESCRIPTION Table 2. Pin Description (for the PLCC52 package - Note 1) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU ...
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Pin Name Pin Type Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low Reset Power-up. These pins make up Port A. These port pins are configurable and can have the following functions: ...
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PSD813F2V, PSD854F2V Pin Name Pin Type PC2 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC2) output. ...
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Pin Name Pin Type PC7 pin of Port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC7) output. PC7 11 ...
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PSD813F2V, PSD854F2V Figure 5. PSD Block Diagram 14/109 Doc ID 10552 Rev 3 AI02861G ...
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PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 5 shows the architecture of the PSD device family. The functions of each block are de- scribed briefly in the following sections. Many of the blocks perform multiple functions ...
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PSD813F2V, PSD854F2V JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, ...
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DEVELOPMENT SYSTEM The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Lan- guage ...
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PSD813F2V, PSD854F2V PSD REGISTER DESCRIPTION AND ADDRESS OFFSET Table 6 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is al- located by the user ...
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DETAILED OPERATION As shown in Figure 5., page 14, the PSD consists of six major types of functional blocks: ■ Memory Blocks ■ PLD Blocks ■ MCU Bus Interface ■ I/O Ports ■ Power Management Unit (PMU) ■ JTAG Interface ...
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PSD813F2V, PSD854F2V Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately ...
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Table 9. Instructions FS0-FS7 or Instruction CSBOOT0- Cycle 1 CSBOOT3 “READ” READ Read Main AAh X555h Flash ID Read Sector AAh@ 1 6,8,13 X555h Protection Program a AAh X555h Flash Byte ...
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PSD813F2V, PSD854F2V INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially de- coded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes ...
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Reading the Erase/Program Status Bits The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends ...
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PSD813F2V, PSD854F2V Data Polling Flag (DQ7) When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the com- plement of the bit being entered for programming/ writing on the DQ7 Bit. Once the Program instruc- tion ...
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PROGRAMMING FLASH MEMORY Flash memory must be erased prior to being pro- grammed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may erase Flash memory all ...
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PSD813F2V, PSD854F2V Data Toggle Checking the Toggle Flag Bit (DQ6 method of determining whether a Program or Erase cycle is in progress or has completed. Figure Data Toggle algorithm. When the MCU issues a Program instruction, the embedded ...
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ERASING FLASH MEMORY Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in If any byte of the Bulk Erase instruction is wrong, the Bulk Erase ...
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PSD813F2V, PSD854F2V SPECIFIC FEATURES Flash Memory Sector Protect Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides addition- al data security because it disables all Program or Erase cycles. This ...
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SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express Configuration. Doc ID 10552 ...
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PSD813F2V, PSD854F2V SECTOR SELECT AND SRAM SELECT Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these ...
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Figure 10. 8031 Memory Modules – Separate Space DPLD RS0 CSBOOT0-3 FS0-FS7 PSEN RD Figure 11. 8031 Memory Modules – Combined Space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT ...
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PSD813F2V, PSD854F2V PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register ...
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PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: ...
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PSD813F2V, PSD854F2V Figure 13. PLD Diagram 34/109 PORTS BUS INPUT PLD Doc ID 10552 Rev 3 I/O ...
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Decode PLD (DPLD) The DPLD, shown in Figure 14, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: ■ 8 Sector Select (FS0-FS7) signals for ...
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PSD813F2V, PSD854F2V Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate ...
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Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. ...
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PSD813F2V, PSD854F2V Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms ...
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Figure 16. CPLD Output Macrocell ARRAY AND BUS INPUT PLD Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 39/109 ...
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PSD813F2V, PSD854F2V Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in 17., page 41. The Input Macrocells (IMC) are ...
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Figure 17. Input Macrocell ARRAY AND BUS INPUT PLD Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V 41/109 ...
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PSD813F2V, PSD854F2V Figure 18. Handshaking Communication Using Input Macrocells 42/109 Doc ID 10552 Rev 3 ...
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MCU BUS INTERFACE The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their Table 16. MCUs and their Control Signals Data Bus MCU Width 8031 8 ...
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PSD813F2V, PSD854F2V PSD Interface to a Multiplexed 8-Bit Bus Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU ...
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PSD Interface to a Non-Multiplexed 8-Bit Bus Figure 20 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO Port, and the data bus is ...
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PSD813F2V, PSD854F2V 80C31 Figure 21 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Se- lect Enable (PSEN, CNTL2), Read ...
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The Intel 80C251 MCU features a user-configu- rable bus interface with four possible bus configu- rations, as shown in Table 18., page The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown ...
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PSD813F2V, PSD854F2V Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD ...
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The Philips 80C51XA MCU family supports 16-bit multiplexed bus that can have burst cy- cles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) ...
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PSD813F2V, PSD854F2V 68HC11 Figure 25 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be Figure 25. Interfacing the PSD with a 68HC11 68HC11 8 ...
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I/O PORTS There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per ...
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PSD813F2V, PSD854F2V Figure 26. General I/O Port Architecture DATA OUT REG ADDRESS D ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) ...
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MCU I/O Mode In the MCU I/O mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The ...
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PSD813F2V, PSD854F2V Table 20. Port Operating Mode Settings Defined in Mode PSDabel MCU I/O Declare pins only PLD I/O Logic equations Data Port (Port A) N/A Address Out Declare pins only (Port A,B) Address In Logic for equation (Port A,B,C,D) ...
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Address In Mode For MCUs that have more than 16 address sig- nals, the higher addresses can be connected to Port and D. The address input can be latched in the Input Macrocell (IMC) by Address Strobe ...
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PSD813F2V, PSD854F2V JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for In- System Programming (ISP). You can multiplex JTAG operations with other functions on Port C because In-System Programming (ISP) is not per- formed in ...
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Table 26. Drive Register Pin Assignment Drive Bit 7 Bit 6 Register Open Open Port A Drain Drain Open Open Port B Drain Drain Open Open Port C Drain Drain 1 1 Port Note ...
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PSD813F2V, PSD854F2V Input Macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See ...
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Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 29): ■ MCU I/O Mode ■ CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or ...
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PSD813F2V, PSD854F2V Port D – Functionality and Structure Port D has three I/O pins. See Figure ure 31., page 61. This port does not support Ad- dress Out mode, and therefore no Control Register is required. Port D can be ...
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External Chip Select The CPLD also provides three External Chip Se- lect (ECS0-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product Figure 31. Port D External ...
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PSD813F2V, PSD854F2V POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ■ All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with ...
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Automatic Power-down (APD) Unit and Power-down Mode The APD Unit, shown in Figure 32, puts the PSD into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on ...
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PSD813F2V, PSD854F2V For Users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compati- ble) in your design, and you wish to use the Pow- er-down ...
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Table 30. Power Management Mode Registers PMMR0 (Note 1) Bit off Automatic Power-down (APD) is disabled. Bit 1 APD Enable Automatic Power-down (APD) is enabled. Bit ...
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PSD813F2V, PSD854F2V PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Ex- press as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O ...
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RESET TIMING AND DEVICE STATUS AT RESET Power-Up Reset Upon Power-up, the PSD requires a Reset (RE- SET) pulse of duration t NLNH-PO steady. During this period, the device loads inter- nal configurations, clears some of the registers and sets ...
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PSD813F2V, PSD854F2V Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register PMMR0 ...
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PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface block can be enabled on Port C (see Table 34., page blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration Register bits may be programmed through the ...
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PSD813F2V, PSD854F2V JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating ...
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INITIAL DELIVERY STATE When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration Register bits are set to ’0.’ The code, configuration, and PLD logic are loaded using the ...
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PSD813F2V, PSD854F2V AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD: ❏ DC Electrical Specification ❏ AC Timing Specification ■ PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell ...
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Table 36. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number ...
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PSD813F2V, PSD854F2V Table 37. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down ...
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... ESD Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi-Z) ...
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PSD813F2V, PSD854F2V DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from ...
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Table 44. Capacitance Symbol Parameter C Input Capacitance (for input pins) IN Output Capacitance (for input/ C OUT output pins) C Capacitance (for CNTL2/V VPP Note: 1. Sampled only, not 100% tested. 2. Typical values are for T = 25°C ...
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PSD813F2V, PSD854F2V Table 45. DC Characteristics (5V devices) Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V ...
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Symbol Parameter V Reset Pin Hysteresis HYS V (min) for Flash Erase and CC V LKO Program V Output Low Voltage OL V Output High Voltage OH I Input Leakage Current LI I Output Leakage Current LO PLD Only Operating ...
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PSD813F2V, PSD854F2V Table 47. CPLD Combinatorial Timing (5V devices) Symbol Parameter CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input to CPLD t EA Output Enable CPLD Input to CPLD t ER Output Disable CPLD Register Clear ...
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Figure 41. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f MAX Internal 1/(t S Feedback (f ) ...
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PSD813F2V, PSD854F2V Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f ) CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time ...
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Figure 42. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 43. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT tARPW tARP tCHA tCLA tSA tHA tCOA Doc ID 10552 Rev 3 PSD813F2V, PSD854F2V AI02864 AI02859 83/109 ...
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PSD813F2V, PSD854F2V Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices) Symbol Parameter Conditions Maximum Frequency 1/(t SA External Feedback Maximum Frequency f Internal 1/(t MAXA SA Feedback (f ) CNTA Maximum Frequency 1/(t CHA Pipelined Data Input Setup ...
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Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices) Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f MAXA Internal 1/(t SA Feedback (f ) CNTA Maximum 1/(t Frequency Pipelined Data Input Setup t SA Time t ...
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PSD813F2V, PSD854F2V Figure 44. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 53. Input Macrocell Timing (5V devices) Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH ...
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Figure 45. READ Timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV Note and t are not required for 80C251 in Page Mode or ...
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PSD813F2V, PSD854F2V Table 55. READ Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid ...
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Table 56. READ Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD ...
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PSD813F2V, PSD854F2V Figure 46. WRITE Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS 90/109 t AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t ...
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Table 57. WRITE Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge ...
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PSD813F2V, PSD854F2V Table 58. WRITE Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to ...
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Table 60. Program, WRITE and Erase Times (3V devices) Symbol Flash Program 1 Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles ...
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PSD813F2V, PSD854F2V Figure 47. Peripheral I/O READ Timing ALE/AS A/D BUS CSI RD Table 61. Port A Peripheral Data Mode READ Timing (5V devices) Symbol Parameter Address Valid to Data t AVQV–PA Valid t CSI Valid to Data Valid SLQV–PA ...
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Table 62. Port A Peripheral Data Mode READ Timing (3V devices) Symbol Parameter t Address Valid to Data Valid AVQV–PA t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode t ...
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PSD813F2V, PSD854F2V Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices) Symbol Parameter Data Propagation Delay WLQV–PA t Data to Port A Data Propagation Delay DVQV– Invalid to Port A Tri-state WHQZ–PA Note: ...
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Figure 50. ISC Timing t TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 67. ISC Timing (5V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, ...
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PSD813F2V, PSD854F2V Table 68. ISC Timing (3V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low Time (except for t ISCCL PLD) t ...
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PACKAGE MECHANICAL In order to meet environmental requirements, ST offers these devices in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing Ne N ...
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PSD813F2V, PSD854F2V Table 71. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 10.00 E2 7.80 e 0.65 L 0.88 L1 1.60 α ...
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Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 72. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions Symbol Typ ...
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PSD813F2V, PSD854F2V Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline QFP-A Note: Drawing is not to scale. 102/109 Doc ID 10552 Rev ...
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Table 73. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data Symb. Typ 0.10 A2 1.40 α 3.5° 16.00 D1 14.00 D2 12.00 E 16.00 E1 14.00 E2 12.00 e 0.80 L 0.60 L1 ...
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PSD813F2V, PSD854F2V PART NUMBERING Table 74. Ordering Information Scheme Example: Device Type PSD8 = 8-bit PSD with Register Logic PSD9 = 8-bit PSD with Combinatorial Logic SRAM Capacity Kbit 5 = 256 Kbit Flash Memory Capacity 3 ...
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APPENDIX A. PQFP52 PIN ASSIGNMENTS Table 75. PQFP52 Connections (Figure 2) Pin Number Pin Assignments ...
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PSD813F2V, PSD854F2V APPENDIX B. PLCC52 PIN ASSIGNMENTS Table 76. PLCC52 Connections (Figure 3) Pin Number Pin Assignments ...
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APPENDIX C. TQFP64 PIN ASSIGNMENTS Table 77. TQFP64 Connections (Figure 4) Pin Number Pin Assignments ...
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PSD813F2V, PSD854F2V REVISION HISTORY Table 78. Document Revision History Date Version 04-Jun-04 1.0 First Edition (3V split from original) Removed PSD853F2V and PSD833F2V root part numbers. Updated Table 1 to remove PSD813F3, PSD813F4, PSD833F2, PSD834F2, and PSD853F2. Updated Table 74 ...
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