LC51024MV-52F484C Lattice, LC51024MV-52F484C Datasheet - Page 86

• Manufacturer Part Number: LC51024MV-52F484C
• Manufacturer: Lattice

Lattice Semiconductor
ispXPLD 51024MX Logic Signal Connections (Continued)
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differen-
tial clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
sysIO
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
LVDS Pair
142N
142P
143N
143P
144N
144P
145N
145P
146N
146P
147N
147P
148N
148P
149N
149P
150N
150P
151N
151P
152N
152P
153N
153P
154N
154P
155N
155P
156N
156P
157N
157P
158N
158P
-
-
-
-
-
-
-
-
Macrocell/Function
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
Y14/VREF0
Primary
VCCO0
VCCO0
VCCO0
AA30
AA28
AA26
AA24
VCC
GND
Y26
Y24
Y22
Y20
Y18
Y16
Y12
Y10
Z30
Z28
Z26
Z24
Z22
Z20
Z18
Z16
Z14
Z12
Z10
Y8
Y6
Y4
Y2
Y0
Z8
Z6
Z4
Z2
Z0
Macrocell 1
AA29
AA28
AA27
AA26
AA25
AA24
AA23
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
AA12
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Alternate Outputs
Y3
Y2
Y1
Y0
-
-
-
-
-
-
-
-
86
Macrocell 2
AA29
AA28
AA27
AA26
AA25
AA24
AA23
AA22
AA21
AA20
AA19
AA18
AA3
AA2
AA1
AA0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ispXPLD 5000MX Family Data Sheet
Alternate
Input
AA31
AA29
AA27
AA25
Y27
Y25
Y23
Y21
Y19
Y17
Y15
Y13
Y11
Z31
Z29
Z27
Z25
Z23
Z21
Z19
Z17
Z15
Z13
Z11
Y9
Y7
Y5
Y3
Y1
Z9
Z7
Z5
Z3
Z1
-
-
-
-
-
-
-
-
GND (Bank 0) GND (Bank 0)
GND (Bank 0) GND (Bank 0)
GND (Bank 0) GND (Bank 0)
Ball Number
484 fpBGA
VCCO0
VCCO0
VCCO0
GND
VCC
C10
D10
B11
A11
F11
F10
E10
B10
A10
C9
D9
C7
D6
D8
D7
C6
C5
C4
D5
A9
F9
E9
A8
B8
A7
B7
A5
B5
B6
E8
E7
E6
F8
F7
Ball Number
672 fpBGA
VCCO0
VCCO0
VCCO0
GND
VCC
A10
B10
C10
C9
C8
C7
C6
C5
C4
D5
D9
D8
D7
D6
G8
G9
A9
A8
A7
A6
A5
A4
A3
B9
B8
B7
B6
B5
B4
B3
F9
E9
F7
F8