EPM7128SQC100-15N Altera, EPM7128SQC100-15N Datasheet - Page 20

• Manufacturer Part Number: EPM7128SQC100-15N
• Description: IC MAX 7000 CPLD 128 100-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7128SQC100-15N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 84
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 8
• Family Name: MAX 7000S
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 84
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Cpld Type: EEPROM
• No. Of Macrocells: 128
• No. Of I/o's: 84
• Propagation Delay: 15ns
• Global Clock Setup Time: 11ns
• Frequency: 76.9MHz
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2038; EPM7128SQC100-15N

MAX 7000 Programmable Logic Device Family Data Sheet
Programmable
Speed/Power
Control
Output
Configuration
20
MAX 7000 devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000
device for either high-speed (i.e., with the Turbo Bit
or low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (t
t
MAX 7000 device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O
interface feature, which allows MAX 7000 devices to interface with
systems that have differing supply voltages. The 5.0-V devices in all
packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCC pins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V V
are therefore compatible with both 3.3-V and 5.0-V inputs.
The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power
supply, depending on the output requirements. When the VCCIO pins are
connected to a 5.0-V supply, the output levels are compatible with 5.0-V
systems. When V
3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices
operating with V
timing delay of t
Open-Drain Output Option (MAX 7000S Devices Only)
MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
EN
, and t
SEXP
, t
CCINT
ACL
OD2
CCIO
CCIO
, and t
level, input voltage thresholds are at TTL levels, and
instead of t
levels lower than 4.75 V incur a nominally greater
is connected to a 3.3-V supply, the output high is
CPPW
parameters.
OD1
.
LPA
) for the t
TM
option turned on)
Altera Corporation
LAD
, t
LAC
, t
IC
,