EPM7128SQC100-15N Altera, EPM7128SQC100-15N Datasheet - Page 50

• Manufacturer Part Number: EPM7128SQC100-15N
• Description: IC MAX 7000 CPLD 128 100-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7128SQC100-15N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 84
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 8
• Family Name: MAX 7000S
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 84
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Cpld Type: EEPROM
• No. Of Macrocells: 128
• No. Of I/o's: 84
• Propagation Delay: 15ns
• Global Clock Setup Time: 11ns
• Frequency: 76.9MHz
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2038; EPM7128SQC100-15N

MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
50
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 36. EPM7192S Internal Timing Parameters (Part 2 of 2)
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
The f
Operating conditions: V
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
The t
running in the low-power mode.
LPA
MAX
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
parameter must be added to the t
values represent the highest frequency for pipelined data.
Parameter
CCIO
= 3.3 V ± 10% for commercial and industrial use.
(7)
(8)
Conditions
LAD
, t
LAC
, t
IC
, t
EN
, t
Min
1.7
2.3
0.7
SEXP
-7
, t
Max
ACL
10.0
Note (1)
1.4
1.2
3.2
3.1
2.5
2.7
2.7
2.4
, and t
Speed Grade
Min
3.0
3.0
0.5
CPPW
-10
Table
LAD
parameters for macrocells
Max
11.0
5.0
2.0
2.0
5.0
1.0
3.0
3.0
1.0
parameter into the signal
14. See
Min
Altera Corporation
4.0
2.0
1.0
Figure 13
-15
LPA
Max
13.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
parameter
for more
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns