DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 43

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
5
Freescale Semiconductor
No.
118 TA setup before RD or WR deassertion
119 TA hold after RD or WR deassertion
All timings for 100 MHz are measured from 0.5 Vcc to .05 Vcc
WS is the number of wait states specified in the BCR.
Timings 100, 107 are guaranteed by design, not tested.
Timing 110, 111, and 112, are not specified for 100 MHz.
In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.
AA0–AA3
A0–A17
D0–D23
WR
RD
TA
Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz
Characteristics
113
Figure 3-11 SRAM Read Access
115
DSP56362 Technical Data, Rev. 4
5
Symbol
104
100
105
116
0.25 × T
Expression
119
C
+ 2.0
Data
External Memory Expansion Port (Port A)
2
In
1
Min
4.5
100 MHz
0
(continued)
117
106
118
Max
—
—
Min
AA0468
4.1
0.0
120 MHz
Max
—
—
Unit
3-17
ns
ns