B300W35A102E1G ON Semiconductor, B300W35A102E1G Datasheet - Page 6

• Manufacturer Part Number: B300W35A102E1G
• Description: IC PROCESSOR AUDIO 24BIT WLCSP
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 300r
• Type: Floating Pointr

Specifications of B300W35A102E1G

• Interface: I²C, PCM, SPI, UART
• Clock Rate: 40MHz
• On-chip Ram: 110kB
• Voltage - I/o: 1.0V, 2.0V
• Voltage - Core: 0.95V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 35-WLCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -

Environmental Characteristics
All BelaSigna 300 package options are Green (RoHS−compliant). Contact ON Semiconductor for supporting documentation.
WLCSP Package Option
SAC266.
Mechanical Information and Circuit Design Guidelines
OSCILLATION CIRCUITRY
DIGITAL INTERFACES
Internal oscillator frequency
Calibrated internal clock
frequency
Internal oscillator jitter
External oscillator tolerances
Maximum working frequency
I2C baud rate
General−purpose UART
baud rate
Table 2. ELECTRICAL SPECIFICATIONS
4. DFN Package option can have higher input−referred noise up to 2 mV worse than the WLCSP. WLCSP specifications listed.
5. CDM only applies to the DFN package.
Table 3. WLCSP PACKAGE−LEVEL QUALIFICATION
Table 4. WLCSP BOARD−LEVEL QUALIFICATION
Moisture sensitivity level
Thermal cycling test (TCT)
Highly accelerated stress
test (HAST)
High temperature stress
test (HTST)
Temperature
All BelaSigna 300 packages are Pb−free, RoHS−compliant and Green.
BelaSigna 300 parts are qualified against standards outlined in the following sections.
The solder ball composition for the WLCSP package is
BelaSigna 300 is available in two packages:
1. A 2.68 x 3.63 mm ultra−miniature wafer−level chip scale package (WLCSP)
2. A 8.9 x 5 mm DFN package
Packaging Level
Board Level
Description
JEDEC Level 1
−55°C to 150°C for 500 cycles
85°C / 85% RH for 1000 hours
150°C for 1000 hours
−40°C to 125°C for 2500
cycles with no failures
SYS_CLK
SYS_CLK
EXT_CLK
Symbol
CLK
MAX
(continued)
System clock: 1.28 MHz
Duty cycle
System clock: 30 MHz
External clock; VBAT: 1.8 V
System clock < 1.6 MHz
System clock > 1.6 MHz
System clock ≥ 5.12 MHz
http://onsemi.com
Conditions
6
DFN Package Option
Contact ON Semiconductor for full details.
Table 5. DFN PACKAGE−LEVEL QUALIFICATION
Table 6. DFN BOARD−LEVEL QUALIFICATION
Moisture sensitivity level
Thermal cycling test (TCT)
Highly accelerated stress
test (HAST)
High temperature stress
test (HTST)
Temperature
The DFN package has been qualified against AEC−Q100.
Packaging Level
Board Level
Min
0.5
−1
45
−
−
−
−
−
Typ
0.4
±0
50
−
−
−
−
−
1
JEDEC Level 3
30°C / 60% RH for 192 hours
−65°C to 150°C for 500 cycles
130°C / 85% RH for 96 hours
150°C for 1000 hours
−40°C to 125°C for 2500
cycles with no failures
10.24
Max
300
100
400
+1
55
40
1
−
Units
Mbps
MHz
MHz
kbps
kbps
ns
ps
%
%
Screened
√
√
√