0W344-004-XTP ON Semiconductor, 0W344-004-XTP Datasheet - Page 5

• Manufacturer Part Number: 0W344-004-XTP
• Description: DSP BELASIGNA 200 AUDIO 52-NQFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 200r
• Type: Fixed Pointr

Specifications of 0W344-004-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 33MHz
• On-chip Ram: 42kB
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-TFQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -
• Voltage - I/o: -
• Voltage - Core: -

BelaSigna 200
digital pads of BelaSigna 200 itself. Analog ground returns associated with the audio output stage should connect back to the star point
on separate individual traces.
For more information on the recommended ground design strategy, see Table 1.
In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be
used. Each analog ground return should connect to the star point with separate traces.
3.2 Internal Power Supplies
Power management circuitry in BelaSigna 200 generates separate digital (VDDC) and analog (VREG, VDBL) regulated supplies. Each
supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors should be placed as
close as possible to the power pads. Further details are provided in Table 1. Non-critical signals are outlined in Table 2.
Table 1: Critical Signal
Pin Name
VBAT
VREG, VDBL
AGND
VDDC
GNDO, GNDC
AI0, AI1 / LOUT, AI2, AI3
AIR
AO0, AO1
RCVR0+, RCVR0-, RCVR1+,
RCVR1-
AOR
RCVRGND
EXT_CLK
AI_RC
Description
Power supply
Internal regulator for analog
sections
Analog ground return
Internal regulator for digital
sections
Digital ground return (pads and
core)
Microphone inputs
Input stage reference voltage
Analog audio output
Direct digital audio output
Output stage reference voltage
Output stage ground return
External clock input / internal
clock output
Infrared receiver input
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Routing Guideline
Place 1μF (min) decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND plane.
Place separate 1μF decoupling capacitors close to each pin. Connect
negative capacitor terminal to AGND. Keep away from digital traces and
output traces. VREG may be used to generate microphone bias. VDBL
shall not be used to supply external circuitry.
Connect to AGND plane.
Place 10μF decoupling capacitor close to pin. Connect negative terminal
of capacitor to DGND. Should be connected to VDDO pins and to
EEPROM power.
Connect to digital ground.
Keep as short as possible. Keep away from all digital traces and audio
outputs. Avoid routing in parallel with other traces. Connect unused inputs
to AGND.
Connect to AGND. If no analog ground plane, should share trace with
microphone grounds to star point.
Keep away from microphone inputs.
Keep away from analog traces, particularly microphone inputs.
Corresponding traces should be of approximately the same length.
Connect to star point. Share trace with power amplifier (if present).
Connect to star point.
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
If used, minimize trace length to photodiode.