EPF81500AQC240-2 Altera, EPF81500AQC240-2 Datasheet - Page 18

IC FLEX 8000A FPGA 16K 240-PQFP

EPF81500AQC240-2

Manufacturer Part Number
EPF81500AQC240-2
Description
IC FLEX 8000A FPGA 16K 240-PQFP
Manufacturer
Altera
Series
FLEX 8000r
Datasheet

Specifications of EPF81500AQC240-2

Number Of Logic Elements/cells
1296
Number Of Labs/clbs
162
Number Of I /o
181
Number Of Gates
16000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 8000
Number Of Usable Gates
16000
Number Of Logic Blocks/elements
1296
# Registers
1500
# I/os (max)
181
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
1296
Ram Bits
8
Device System Gates
16000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2249

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Price
Part Number:
EPF81500AQC240-2
Manufacturer:
ALTERA
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Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPF81500AQC240-2
Manufacturer:
ALTERA
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EPF81500AQC240-2
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Part Number:
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Manufacturer:
ALTERA
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Manufacturer:
ALTERA
0
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 9. FLEX 8000 Device Interconnect Resources
18
1
1
8
8
Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.
LAB Local
Interconnect
IOE
IOE
IOE
IOE
Column
Interconnect
LAB
LAB
A1
B1
IOE
IOE
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. The
MAX+PLUS II Compiler uses the programmable inversion option to
automatically invert signals from the row and column interconnect where
appropriate.
IOE
IOE
Cascade &
Carry Chain
Row
Interconnect
Figure 10
LAB
LAB
A2
B2
shows the IOE block diagram.
IOE
IOE
IOE
IOE
See Figure 12
for details.
IOE
IOE
IOE
IOE
Altera Corporation
1
1
8
8
See Figure 11
for details.

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