EPF81500AQC240-2 Altera, EPF81500AQC240-2 Datasheet - Page 33

• Manufacturer Part Number: EPF81500AQC240-2
• Description: IC FLEX 8000A FPGA 16K 240-PQFP
• Manufacturer: Altera
• Series: FLEX 8000r

Specifications of EPF81500AQC240-2

• Number Of Logic Elements/cells: 1296
• Number Of Labs/clbs: 162
• Number Of I /o: 181
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: FLEX 8000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1296
• # Registers: 1500
• # I/os (max): 181
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1296
• Ram Bits: 8
• Device System Gates: 16000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2249

Altera Corporation
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Table 17. FLEX 8000 Internal Timing Parameters
IOD
IOC
IOE
IOCO
IOCOMB
IOSU
IOH
IOCLR
IN
OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
Table 18. FLEX 8000 LE Timing Parameters
LUT
CLUT
RLUT
GATE
CASC
CICO
CGEN
CGENR
C
CH
CL
CO
COMB
SU
H
PRE
CLR
Symbol
Symbol
IOE register data delay
IOE register control signal delay
Output enable delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time before clock; IOE register recovery time after asynchronous clear
IOE register hold time after clock
IOE register clear delay
Input pad and buffer delay
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF
Output buffer disable delay, C1 = 5 pF
Output buffer enable delay, slow slew rate = off, V
Output buffer enable delay, slow slew rate = off, V
Output buffer enable delay, slow slew rate = on, C1 = 35 pF
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Cascade gate delay
Cascade chain routing delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
LE register control signal delay
LE register clock high time
LE register clock low time
LE register clock-to-output delay
Combinatorial delay
LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or
load
LE register hold time after clock
LE register preset delay
LE register clear delay
FLEX 8000 Programmable Logic Device Family Data Sheet
Note (1)
Note (1)
Parameter
Parameter
CCIO
CCIO
CCIO
CCIO
= 5.0 V, C1 = 35 pF
= 3.3 V, C1 = 35 pF
= 5.0 V C1 = 35 pF
= 3.3 V C1 = 35 pF
(3)
(3)
(2)
(2)
(2)
(2)
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