EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 132

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

I/O Structure
2–124
Stratix II GX Device Handbook, Volume 1
f
These dedicated circuits combined, with enhanced PLL clocking and
phase-shift ability, provide a complete hardware solution for interfacing
to high-speed memory.
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices
volume 2 of the Stratix II GX Device Handbook.
Programmable Drive Strength
The output buffer for each Stratix II GX device I/O pin has a
programmable drive strength control for certain I/O standards. The
LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of drive
strength that you can control. The default setting used in the Quartus II
software is the maximum current strength setting that is used to achieve
maximum I/O performance. For all I/O standards, the minimum setting
is the lowest drive strength that guarantees the I
Using minimum settings provides signal slew rate control to reduce
system noise and signal overshoot.
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