EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 31

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

Altera Corporation
October 2007
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter.
Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user
programmable value, the rx_rlv signal goes high for a minimum pulse
width of two recovered clock cycles. The maximum run values supported
are shown in
Running Disparity Check
The running disparity error rx_disperr and running disparity value
rx_runningdisp are sent along with aligned data from the 8B/10B
decoder to the FPGA. You can ignore or act on the reported running
disparity value and running disparity error signals.
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in
bit-slip mode.
The bit-slip mode provides the option to manually shift the word
boundary through the FPGA. This feature is useful for:
■
■
■
This feature can be applied at 10-bit and 16-bit data widths.
The word aligner outputs a word boundary as it is received from the
analog receiver after reset. You can examine the word and search its
boundary in the FPGA. To do so, assert the rx_bitslip signal. The
rx_bitslip signal should be toggled and held constant for at least two
FPGA clock cycles.
For every rising edge of the rx_bitslip signal, the current word
boundary is slipped by one bit. Every time a bit is slipped, the bit received
earliest is lost. If bit slipping shifts a complete round of bus width, the
word boundary is back to the original boundary.
Single-Width
Double-Width
Table 2–7. Maximum Run Length (UI)
Longer synchronization patterns than the pattern detector can
accommodate
Scrambled data stream
Input stream consisting of over-sampled data
Mode
Table
8 Bit
2–7.
128
—
10 Bit
Stratix II GX Device Handbook, Volume 1
160
—
PMA Serialization
16 Bit
512
Stratix II GX Architecture
—
20 Bit
640
—
2–23