EP2S60F672C4N Altera, EP2S60F672C4N Datasheet - Page 63

• Manufacturer Part Number: EP2S60F672C4N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672C4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1913; EP2S60F672C4N

Altera Corporation
May 2007
Figure 2–38. Regional Clock Control Blocks
Notes to
(1)
(2)
(3)
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select
blocks.The clock outputs from corner PLLs cannot be dynamically selected
through the global clock control block.
The clock outputs from corner PLLs cannot be dynamically selected through the
global clock control block.
Figure
PLL Counter
2–38:
Outputs
(3)
2
CLKp
Pin
Enable/
Disable
RCLK
CLKn
Pin
Stratix II Device Handbook, Volume 1
(2)
Internal
Logic
Static Clock Select (1)
Internal
Logic
Stratix II Architecture
2–55