EP1C12F256C6 Altera, EP1C12F256C6 Datasheet - Page 42

• Manufacturer Part Number: EP1C12F256C6
• Description: IC CYCLONE FPGA 12K LE 256-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C12F256C6

• Number Of Logic Elements/cells: 12060
• Number Of Labs/clbs: 1206
• Total Ram Bits: 239616
• Number Of I /o: 185
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 12060
• # I/os (max): 185
• Frequency (max): 405.2MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 12060
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1788; EP1C12F256C6

Cyclone Device Handbook, Volume 1
2–36
Preliminary
External Clock Inputs
Each PLL supports single-ended or differential inputs for source-
synchronous receivers or for general-purpose use. The dedicated clock
pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also
act as LVDS input pins. See
Table 2–8
pins.
For more information on LVDS I/O support, refer to
page
External Clock Outputs
Each PLL supports one differential or one single-ended output for
source-synchronous transmitters or for general-purpose external clocks.
If the PLL does not use these PLL_OUT pins, the pins are available for use
as general-purpose I/O pins. The PLL_OUT pins support all I/O
standards shown in
The external clock outputs do not have their own V
supplies. Therefore, to minimize jitter, do not place switching I/O pins
next to these output pins. The EP1C3 device in the 100-pin TQFP package
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
LVDS
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
SSTL-3 class II
Differential SSTL-2
Table 2–8. PLL I/O Standards
2–54.
I/O Standard
shows the I/O standards supported by PLL input and output
Table
2–8.
Figure
2–25.
CLK Input
v
v
v
v
v
v
v
v
v
v
—
CC
“LVDS I/O Pins” on
and ground voltage
Altera Corporation
EXTCLK Output
v
v
v
v
v
v
v
v
v
v
v
May 2008