EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 66

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–58
Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
f
f
f
f
f
t
IN
INPFD
VCO
INDUTY
EINDUTY
INCCJ
(4)
Symbol
(3),
Core Performance Specifications for the Arria II Device Family
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–4 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–5 Speed Grade)
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–6 Speed Grade)
Input frequency to the PFD
PLL VCO operating Range
Input clock duty cycle
External feedback clock input duty cycle
Input clock cycle-to-cycle jitter (Frequency  100 MHz)
Input clock cycle-to-cycle jitter (Frequency  100 MHz)
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), embedded memory, configuration, and JTAG specifications for
Arria II GX and GZ devices.
Clock Tree Specifications
Table 1–42
Table 1–42. Clock Tree Performance for Arria II GX Devices
Table 1–43
Table 1–43. Clock Tree Performance for Arria II GZ Devices
PLL Specifications
Table 1–44
GCLK and RCLK
GCLK and RCLK
Clock Network
Clock Network
PCLK
PCLK
lists the clock tree specifications for Arria II GX devices.
lists the clock tree specifications for Arria II GZ devices.
lists the PLL specifications for Arria II GX devices.
Description
(2)
I3, C4
500
420
–C3 and –I3
700
500
Performance
Performance
C5,I5
500
350
Min
600
40
40
—
—
Chapter 1: Device Datasheet for Arria II Devices
5
5
5
5
–C4 and –I4
Typ
—
—
—
—
—
—
—
—
—
500
450
December 2010 Altera Corporation
400
280
C6
670
622
500
1,400
±750
Max
0.15
325
60
60
Switching Characteristics
(1)
(1)
(1)
ps (p–p)
UI (p–p)
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
Unit
%
%