EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 47

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 2–17. M4K RAM Block Control Signals
Figure 2–18. M4K RAM Block LAB Row Interface
Altera Corporation
July 2005
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 and C8
Interconnects
8
clock_a
M4K RAM Block Local
Interconnect Region
10
clocken_a
renwe_a
Byte enable
Clocks
address
LAB Row Clocks
alcr_a
M4K RAM
Block
datain
alcr_b
dataout
Signals
Control
renwe_b
clocken_b
Stratix Device Handbook, Volume 1
8
clock_b
Stratix Architecture
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 and R8
Interconnects
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
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