EP2S130F1020I4 Altera, EP2S130F1020I4 Datasheet - Page 69

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EP2S130F1020I4

Manufacturer Part Number
EP2S130F1020I4
Description
IC STRATIX II FPGA 130K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S130F1020I4

Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1786

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Altera Corporation
May 2007
Figure 2–41. Global & Regional Clock Connections from Center Clock Pins &
Fast PLL Outputs
Notes to
(1)
(2)
EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the
connectivity from these four PLLs to the global and regional clock networks
remains the same as shown.
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Figure
2–41:
Note (1)
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–61

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