XCV812E-6BG560C Xilinx Inc, XCV812E-6BG560C Datasheet - Page 18

• Manufacturer Part Number: XCV812E-6BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6BG560C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 404
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Dc: 0325
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
Module 2 of 4
14
PROGRAM
(Output)
DOUT
CCLK
Figure 14: Slave-Serial Mode Programming Switching Characteristics
DIN
M2
PROGRAM
DONE
Figure 13: Master/Slave Serial Mode Circuit Diagram
M0 M1
VIRTEX-E
MASTER
SERIAL
1 T
DOUT
CCLK
DCC
DIN
INIT
2 T
3 T
3.3V
CCD
CCO
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4.7 K
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4 T
(Low Reset Option Used)
CCH
CLK
DATA
CE
RESET/OE
XC1701L
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.
Figure 13
the left-most device operates in master-serial mode. The
remaining devices operate in slave-serial mode. The SPROM
RESET pin is driven by INIT, and the CE input is driven by
DONE. There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
CEO
N/C
shows a full master/slave system. In this system,
5 T
CCLK
PROGRAM
DIN
DONE
M2
M0 M1
CCL
N/C
XC4000XL,
VIRTEX-E,
SLAVE
DOUT
INIT
XCVE_ds_013
DS025-2 (v2.3) November 19, 2002
X5379_a
R