XCV812E-6BG560C Xilinx Inc, XCV812E-6BG560C Datasheet - Page 35

• Manufacturer Part Number: XCV812E-6BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6BG560C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 404
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Dc: 0325
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Verilog Initialization Example
module MYMEM (CLK, WE, ADDR, DIN, DOUT);
input CLK, WE;
input [8:0] ADDR;
input [7:0] DIN;
output [7:0] DOUT;
wire logic0, logic1;
//synopsys dc_script_begin
//set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
//set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
//synopsys dc_script_end
assign logic0 = 1’b0;
assign logic1 = 1’b1;
RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),
.DO(DOUT));
//synopsys translate_off
defparam ram0.INIT_00 =
256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;
defparam ram0.INIT_01 =
256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;
//synopsys translate_on
endmodule
Using SelectI/O
The Virtex-E FPGA series includes a highly configurable,
high-performance I/O resource, called SelectI/O™ to pro-
vide support for a wide variety of I/O standards. The
SelectI/O resource is a robust set of features including pro-
grammable control of output drive strength, slew rate, and
input delay and hold time. Taking advantage of the flexibility
and SelectI/O features and the design considerations
described in this document can improve and simplify sys-
tem level design.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high perfor-
mance I/O becomes more important. While chip-to-chip
delays have an increasingly substantial impact on overall
system speed, the task of achieving the desired system per-
formance becomes more difficult with the proliferation of
low-voltage I/O standards.
SelectI/O, the revolutionary input/output resource of Vir-
tex-E devices, has resolved this potential problem by provid-
ing a highly configurable, high-performance alternative to
the I/O resources of more conventional programmable
devices. The Virtex-E SelectI/O features combine the flexi-
bility and time-to-market advantages of programmable logic
DS025-2 (v2.3) November 19, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
with the high performance previously available only with
ASICs and custom ICs.
Each SelectI/O block can support up to 20 I/O standards.
Supporting such a variety of I/O standards allows the support
of a wide variety of applications, from general purpose stan-
dard applications to high-speed low-voltage memory busses.
SelectI/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL out-
put buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak “keeper” circuit ideal for
use in external bussing applications.
Each input/output block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
The input buffer has an optional delay element used to guar-
antee a zero hold time requirement for input signals regis-
tered within the IOB.
The Virtex-E SelectI/O features also provide dedicated
resources for input reference voltage (V
source voltage (V
system that simplifies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the SelectI/O features, sys-
tem-level design and board design can be greatly simplified
and improved.
CCO
), along with a convenient banking
REF
) and output
Module 2 of 4
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