XC5VLX220-2FFG1760C Xilinx Inc, XC5VLX220-2FFG1760C Datasheet - Page 104

IC FPGA VIRTEX-5 220K 1760FBGA

XC5VLX220-2FFG1760C

Manufacturer Part Number
XC5VLX220-2FFG1760C
Description
IC FPGA VIRTEX-5 220K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr

Specifications of XC5VLX220-2FFG1760C

Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7077888
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
800
Ram Bits
7077888
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX220-2FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220-2FFG1760C
Manufacturer:
XILINX
0
Part Number:
XC5VLX220-2FFG1760C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Chapter 3: Phase-Locked Loops (PLLs)
Reference Clock Switching
104
X-Ref Target - Figure 3-8
All “O” counters are equivalent, anything O0 can do, O1 can do. The PLL outputs are
flexible when connecting to the global clock network since they are identical. In most cases,
this level of detail is imperceptible to the designer as the software and PLL Wizard
determines the proper settings through the PLL attributes and Wizard inputs.
The PLL reference clock can be dynamically switched by using the CLKINSEL pin. The
switching is done asynchronously. Since the clock signal can generate a narrow pulse
resulting in erroneous behavior of the PLL, the PLL should be held in RESET while
selecting the alternate clock with the CLKINSEL (CLKSRC) signal. The PLL clock mux
switching is shown in
mux. No synchronization logic is present.
X-Ref Target - Figure 3-9
8 Phases
Counter
Outputs
VCO
135°
180°
225°
270°
315°
45°
90°
O0
O1
O2
O3
One Cycle Delay
Figure
CLKSRC
CLKIN1
CLKIN2
www.xilinx.com
IBUFG
IBUFG
Figure 3-8: Selecting VCO Phases
BUFG
BUFG
Figure 3-9: Input Clock Switching
DCM
DCM
3-9. The CLKINSEL (CLKSRC) signal directly controls the
ug190_3_09_050906
PLL
CLKIN
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_03_08_032506

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